NRF52810-QCAA-R datasheet(293/483 Pages) NORDIC

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Peripherals

TIFS is only enforced if END_DISABLE and DISABLED_TXEN or END_DISABLE and DISABLED_RXEN shortcuts

are enabled. TIFS is only qualified for use in BLE_1MBIT mode, and default ramp-up mode. The use of

shortcuts and timing is illustrated in Ramp up and TIFS Timing Details on page 293.

TXRU

S0 L S1

PAYLOAD

CRC

TXDISABLE

’1’

RXRU

S0 L S1

PAYLOAD

CRC

RXDISABLE

’X’

DISABLED

TIFS

tTXEN

tRXEN

Figure 69: Ramp up and TIFS Timing Details

6.14.12 Device address match

The device address match feature is tailored for address white listing in a Bluetooth® Smart and similar

implementations.

This feature enables on-the-fly device address matching while receiving a packet on air. This feature only

works in receive mode and as long as the radio is configured for little endian, see PCNF1.ENDIAN.

The device address match unit assumes that the 48 first bits of the payload is the device address and that

bit number 6 in S0 is the TxAdd bit. See the Bluetooth® Core Specification for more information about

device addresses, TxAdd and whitelisting.

The radio is able to listen for eight different device addresses at the same time. These addresses are

specified in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the

DACNF register. The DAB register specifies the 32 least significant bits of the device address, while the DAP

Each of the device addresses can be individually included or excluded from the matching mechanism. This

is configured in the DACNF register.

6.14.13 Bit counter

Radio implements a simple counter that can be configured to generate an event after a specific number of

bits have been transmitted or received.

By using shortcuts, this counter can be started from different events generated by the radio and hence

count relative to these.

The bit counter is started by triggering the BCSTART task, and stopped by triggering the BCSTOP task. A

BCMATCH event will be generated when the bit counter has counted the number of bits specified in the

BCC register. The bit counter will continue to count bits until the DISABLED event is generated or until the

BCSTOP task is triggered. The CPU can therefore, after a BCMATCH event, reconfigure the BCC value for

new BCMATCH events within the same packet.

The bit counter can only be started after the radio has received the ADDRESS event.

The bit counter will stop and reset on BCSTOP, STOP, END and DISABLE tasks.

The figure below illustrates how the bit counter can be used to generate a BCMATCH event in the

beginning of the packet payload, and again generate a second BCMATCH event after sending 2 bytes (16

bits) of the payload.

4430_161 v1.0

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