NRF52810-QCAA-R datasheet(51/483 Pages) NORDIC

51 / 483 page

Core components

DAP

CPU

ARM Cortex-M4

SWDCLK

SWDIO

SW-DP

POWER

CxxxPWRUPREQ

CxxxPWRUPRACK

Power

External

Debugger

Peripherals

RAM & flash

APB/AHB

AHB

AHB-AP

DAP bus

interconnect

APPROTECT.PALL

CTRL-AP

UICR

NVMC

Figure 7: Overview

The main features of the debug system are:

• Two-pin Serial Wire Debug (SWD) interface

• Flash Patch and Breakpoint Unit (FPB) supports:

• Two literal comparators

• Six instruction comparators

4.8.1 DAP - Debug Access Port

An external debugger can access the device via the DAP.

The DAP implements a standard ARM® CoreSight™ Serial Wire Debug Port (SW-DP).

The SW-DP implements the Serial Wire Debug protocol (SWD) that is a two-pin serial interface, see

SWDCLK and SWDIO in Overview on page 51.

In addition to the default access port in the CPU (AHB-AP), the DAP includes a custom Control Access Port

(CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control Access Port on page 51.

Important:

• The SWDIO line has an internal pull-up resistor.

• The SWDCLK line has an internal pull-down resistor.

4.8.2 CTRL-AP - Control Access Port

The Control Access Port (CTRL-AP) is a custom access port that enables control of the device even if the

other access ports in the DAP are being disabled by the access port protection.

Access port protection blocks the debugger from read and write access to all CPU registers and memory-

mapped addresses. See the UICR register APPROTECT on page 47 for more information about

enabling access port protection.

This access port enables the following features:

• Soft reset, see Reset on page 65 for more information

• Disable access port protection

4430_161 v1.0

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