NRF52810-QCAA-R datasheet(137/483 Pages) NORDIC

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Peripherals

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

P O N M L K J I H G F E D C B A

Reset 0x00000000

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RW Field

Value Id

Value

Description

Enabled

Read: Enabled

6.7.2 Electrical specification

6.7.2.1 EGU Electrical Specification

Symbol

Description

Min.

Typ.

Max.

Units

tEGU,EVT

Latency between setting an EGU event flag and the system

setting an interrupt

cycles

6.8 GPIO — General purpose input/output

The general purpose input/output pins (GPIOs) are grouped as one or more ports with each port having up

to 32 GPIOs.

The number of ports and GPIOs per port might vary with product variant and package. Refer to Registers

on page 139 and Pin assignments on page 461 for more information about the number of GPIOs that

are supported.

GPIO has the following user-configurable features:

• Up to 32 GPIO pins per GPIO port

• Configurable output drive strength

• Internal pull-up and pull-down resistors

• Wake-up from high or low level triggers on all pins

• Trigger interrupt on state changes on any pin

• All pins can be used by the PPI task/event system

• One or more GPIO outputs can be controlled through PPI and GPIOTE channels

• All pins can be individually mapped to interface blocks for layout flexibility

• GPIO state changes captured on SENSE signal can be stored by LATCH register

The GPIO port peripheral implements up to 32 pins,

PIN0 through PIN31. Each of these pins can be

individually configured in the PIN_CNF[n] registers (n=0..31).

The following parameters can be configured through these registers:

• Direction

• Drive strength

• Enabling of pull-up and pull-down resistors

• Pin sensing

• Input buffer disconnect

• Analog input (for selected pins)

The PIN_CNF registers are retained registers. See POWER — Power supply on page 61 chapter for more

information about retained registers.

6.8.1 Pin configuration

Pins can be individually configured, through the SENSE field in the PIN_CNF[n] register, to detect either a

high level or a low level on their input.

4430_161 v1.0

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