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NRF52811-QCAA-R7 bảng dữ liệu(PDF) 129 Page - Nordic Semiconductor |
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NRF52811-QCAA-R7 bảng dữ liệu(HTML) 129 Page - Nordic Semiconductor |
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129 / 444 page ![]() Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D D B B B B B A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID Access Field Value ID Value Description High 1 Task mode: Initial value of pin before task triggering is high 6.9.5 Electrical specification 6.10 PDM — Pulse density modulation interface The pulse density modulation (PDM) module enables input of pulse density modulated signals from external audio frontends, for example, digital microphones. The PDM module generates the PDM clock and supports single-channel or dual-channel (Left and Right) data input. Data is transferred directly to RAM buffers using EasyDMA. Listed here are the main features for PDM: • Up to two PDM microphones configured as a Left/Right pair using the same data input • 16 kHz output sample rate, 16-bit samples • EasyDMA support for sample buffering • HW decimation filters The PDM module illustrated in PDM module on page 129 is interfacing up to two digital microphones with the PDM interface. It implements EasyDMA, which relieves real-time requirements associated with controlling the PDM slave from a low priority CPU execution context. It also includes all the necessary digital filter elements to produce PCM samples. The PDM module allows continuous audio streaming. DIN CLK Band-pass and Decimation (right) Band-pass and Decimation (left) Master clock generator PDM to PCM PDM to PCM Figure 41: PDM module 6.10.1 Master clock generator The FREQ field in the master clock's PDMCLKCTRL register allows adjusting the PDM clock's frequency. The master clock generator does not add any jitter to the HFCLK source chosen. It is recommended (but not mandatory) to use the Xtal as HFCLK source. 6.10.2 Module operation By default, bits from the left PDM microphone are sampled on PDM_CLK falling edge, bits for the right are sampled on the rising edge of PDM_CLK, resulting in two bitstreams. Each bitstream is fed into a digital filter which converts the PDM stream into 16-bit PCM samples, and filters and down-samples them to reach the appropriate sample rate. 4454_140 v1.0 129 |
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