ML22Q533 datasheet(38/178 Pages) ROHM

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FEDL22Q53X-02

ML22Q53X

 Watchdog timer overflow detection

A communication error between the HOST MCU and this LSI (disconnection or short-circuit of the MCU command

interface, etc.) can be detected.

Set the watchdog timer overflow detection with WDTEN bit of the SAFE command.

When the detection operation is started, the detection does not stop even if the WDTEN bit is set to "0".

After the detection operation starts, clear the WDT counter with the WDTCL command before the WDT counter

overflows.

When the WDT counter overflows (for the first time), the error bit (WDTERR) is set to "1".

Error bit (WDTERR) can be read with RDERR command. In addition, the error bit (WDTERR) can be cleared by the

ERRCL command after the WDTCL command.

The count time of the WDT counter is 2s the initial value. The counting time can be set to 125ms, 500ms, 2s, 4s. In addition,

it is possible to shift to the command wait state after power-up by the second overflow of the WDT counter.

The count time and the second overflow operation can be set with the dedicated tools (Speech LSI Utility).

*1 Misoperation detection and failure detection outputs are selected by OUTSTAT command.

Recommended Operation Flow of Watchdog Timer

WDTEN

Set WDTEN = "1"

Count-up

WDT counter

WDT overflow

WDTERR

RSTERR

Command

SAFE

WDTCL

Count-up

STATUSn pin

*1 n:1 or 2

Clears the WDT counter by WDTCL commands.

Status

Stop WDT

WDT operation

Signal to shift command

standby state after power-up

WDTCL

Count-up

WDTCL

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ML22Q533 bảng dữ liệu(PDF) 38 Page - Rohm