CDCE72010 datasheet(24/70 Pages) TI

24 / 70 page

CDCE72010

SCAS858 – JUNE 2008...................................................................................................................................................................................................... www.ti.com

SPI

RAM

POWER UP

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

BIT

CONDITION

Address 0

Address 1

Address 2

Address 3

When set to 0, the REF-clock frequency detector is ON

DIS_FDET_REF

PLL Freq. Detect

EEPROM

When set to 1, it is switched OFF

When set to 1, the feedback path frequency detector is switched OFF

DIS_FDET_FB

Diagnostics

EEPROM

(TI Test-GTME)

BIAS_DIV01<0>

When BIAS_DIV01<1:0> =

Output Divider

00, No current reduction for all output-divider

EEPROM

0 and 1

01, Current reduction for all output-divider by about 20%

BIAS_DIV01<1>

10, Current reduction for all output-divider by about 30%

BIAS_DIV23<0>

When BIAS_DIV23<1:0> =

Output Divider

00, No current reduction for all output-divider

EEPROM

2 and 3

01, Current reduction for all output-divider by about 20%

BIAS_DIV23<1>

10, Current reduction for all output-divider by about 30%

PH3ADJC0

PH3ADJC1

PH3ADJC2

PH3ADJC3

Output 3

Coarse phase adjust select for Output Divider 3

EEPROM

PH3ADJC4

PH3ADJC5

PH3ADJC6

OUT3DIVRSEL0

OUT3DIVRSEL1

OUT3DIVRSEL2

Output Divider 3 ratio select

OUT3DIVRSEL3

Output 3

EEPROM

(seeTable 7)

OUT3DIVRSEL4

OUT3DIVRSEL5

OUT3DIVRSEL6

When set to 0, the divider is disabled

EN3DIV

Output 3

EEPROM

When set to 1, the divider is enabled

PECL3HISWING

Output 3

High Output Voltage Swing in LVPECL Mode if set to 1

EEPROM

CMOSMODE3PX

LVCMOS mode select for OUTPUT 3 Positive Pin.

Output 3

EEPROM

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

CMOSMODE3PY

CMOSMODE3NX

LVCMOS mode select for OUTPUT 3 Negative Pin.

Output 3

EEPROM

(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State

CMOSMODE3NY

RAM BITS

OUTPUT TYPE

OUTBUFSEL3X

Output 3

EEPROM

LVPECL

LVDS

OUTBUFSEL3Y

Output 3

LVCMOS

See Settings Above(1)

EEPROM

All Outputs Disabled

(1)

Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs

Submit Documentation Feedback

Product Folder Link(s): CDCE72010

CDCE72010 bảng dữ liệu(PDF) 24 Page - Texas Instruments

CDCE72010 bảng dữ liệu(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

bảng dữ liệu tải về

Link URL