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CDCE72010 bảng dữ liệu(PDF) 35 Page - Texas Instruments

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tên linh kiện CDCE72010
Giải thích chi tiết về linh kiện  Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
PDF  70 Pages
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
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CDCE72010 bảng dữ liệu(HTML) 35 Page - Texas Instruments

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CONFIGURATION DEFAULT MODE
EEPROM
PLL_LOCK
REF_SEL
POWERDOWN
RESET
HOLD
or
MODE_SEL
AUX_SEL
SPI_MISO
SPI_LE(CD1)
SPI_CLK(CD2)
SPI_MOSI(CD3)
Interface
&Control
RAMResistors
PLL_LOCK
REF_SEL
POWERDOWN
RESET
HOLD
or
MODE_SEL
AUX_SEL
CD1
CD2
CD3
EEPROM
Interface
&Control
RAMResistors
CDCE72010
www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The CDCE72010 has two modes of operation, SPI Interface and Configuration Default Mode. The Configuration
Default mode is selected when MODE_SELECT Pin is driven low and it is used where SPI interface is not
available. In the CD Mode configuration, the SPI interface Pins become static control pins CD1, CD2, CD3 and
AUX_SEL as shown in the Pin description. The CD Mode signals are sampled only at power up or after Power
Down are asserted.
In CD Mode BYPASS, CD1 and CD2 are used to switch between EEPROM saved configurations. -CD1 allows
swapping Divider and Phase Adjust value between output couples.
• CD2 allows changing the output type for each output.
• AUX_SEL Controls the Output Mux between VCXO and AUX Input.
• CD3 must be grounded in CD Mode.
Without any interface a single device with a single program can have multiple configurations that can be
implemented on more than one socket.
Figure 13. Writing to EEPROM via SPI Bus in
Figure 14. Using CD1, CD2 to Control What is Copied
Manufacutring,
From EEPROM Into RAM Registers at Power Up
3rd Party Vendor or at TI Test
Copyright © 2008, Texas Instruments Incorporated
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