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CDCE72010 bảng dữ liệu(PDF) 43 Page - Texas Instruments |
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CDCE72010 bảng dữ liệu(HTML) 43 Page - Texas Instruments |
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43 / 70 page  CDCE72010 www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008 Register 7: CD Mode SPI RAM RELATED POWER UP BIT NAME DESCRIPTION/FUNCTION BIT BIT BLOCK CONDITION 0 A0 Address 0 1 1 A1 Address 1 1 2 A2 Address 2 1 3 A3 Address 3 0 4 0 LOCKW 0 Lock-detect window bit 0 (Refer to Reg 9 RAM Bits 6 and 7) 5 1 LOCKW 1 Lock-detect window bit 1 (Refer to Reg 9 RAM Bits 6 and 7) 6 2 RESERVED Set to 0 LOCK-DET EEPROM 7 3 LOCKC0 Number of coherent lock events bit 0 8 4 LOCKC1 Number of coherent lock events bit 1 9 5 ADLOCK Selects Digital PLL_LOCK 0 ,Selects Analog PLL_LOCK 1 10 6 PH7ADJC0 11 7 PH7ADJC1 12 8 PH7ADJC2 13 9 PH7ADJC3 Output 7 Coarse phase adjust select for output divider 7 EEPROM 14 10 PH7ADJC4 15 11 PH7ADJC5 16 12 PH7ADJC6 17 13 OUT7DIVRSEL0 18 14 OUT7DIVRSEL1 19 15 OUT7DIVRSEL2 OUTPUT DIVIDER 7 Ratio Select 20 16 OUT7DIVRSEL3 Output 7 EEPROM (See Table 7) 21 17 OUT7DIVRSEL4 22 18 OUT7DIVRSEL5 23 19 OUT7DIVRSEL6 When set to 0, the divider is disabled 24 20 EN7DIV Output 7 EEPROM When set to 1, the divider is enabled 25 21 PECL7HISWING Output 7 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM CD1 PIN is high and DIVPHA7CD1H is set to low Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 7 26 22 DIVPHA7CD1H CD1 High EEPROM CD1 PIN is high and DIVPHA7CD1H is set to high Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 7 CD1 PIN is low and DIVPHA7CD1L is set to low Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 7 27 23 DIVPHA7CD1L CD1 Low EEPROM CD1 PIN is low and DIVPHA7CD1L is set to high Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 7 28 24 OUTBUF7CD2LX Output Buffer 7 Signaling Selection when CD2 in low CD2 Low EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 29 25 OUTBUF7CD2LY 30 26 OUTBUF7CD2HX Output Buffer 7 Signaling Selection when CD2 in high CD2 High EEPROM (X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable 31 27 OUTBUF7CD2HY Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Link(s): CDCE72010 |
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