CDCE72010 datasheet(5/70 Pages) TI

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PACKAGE THERMAL RESISTANCE FOR QFN (RGZ) PACKAGE

(1) (2)

ABSOLUTE MAXIMUM RATINGS

CDCE72010

www.ti.com...................................................................................................................................................................................................... SCAS858 – JUNE 2008

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

U0P:U0N

7,6

U1P:U1N

10,9

U2P:U2N

13,12

U3P:U3N

21,20

The main outputs of the CDCE72010 are user definable and can be any combination of up

U4P:U4N

24,23

to 9 LVPECL outputs, 9 LVDS outputs, or up to 18 LVCMOS outputs. The outputs are

U5P:U5N

27,26

selectable via the SPI interface. The power-up setting is EEPROM configurable.

U6P:U6N

30,29

U7P:U7N

36,35

U8P:U8N

39,38

Positive universal output buffer 9 can be 3-stated and used as a positive universal auxiliary

U9P or AUXINP

I/O

input buffer (It requires external termination). The auxiliary input signal can be routed to

drive the outputs or the feedback loop to the PLL.

Negative universal output buffer 9 can be 3-stated and used as a negative universal

U9N or AUXINN

I/O

auxiliary input buffer (It requires external termination). The auxiliary input signal can be

routed to drive the outputs or the feedback loop to the PLL.

AIRFLOW

JP (°C/W)

(3)

JA (°C/W)

(LFM)

JEDEC compliant board (6×6 VIAs on PAD)

1.5

100

JEDEC compliant board (6×6 VIAs on PAD)

1.5

17.6

Recommended layout (10×10 VIAs on PAD)

1.5

22.8

100

Recommended layout (10×10 VIAs on PAD)

1.5

13.8

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(2)

Connected to GND with 9 thermal vias (0.3 mm diameter).

(3)

JP (Junction – Pad) is used for the QFN package, because the main heat flow is from the junction to the GND-pad of the QFN.

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VCC,

AVCC,

Supply voltage range(1)

–0.5

4.6

VCC_CP

Input voltage range(2)

–0.5 VCC + 0.5

Output voltage range(2)

–0.5 VCC + 0.5

Input current

VI < 0, VI > VCC

±20

Output current for LVPECL/LVCMOS Outputs

0 < VO < VCC

±50

Junction temperature

125

°C

Tstg

Storage temperature range

–65

150

°C

(1)

All supply voltages have to be supplied simultaneously.

(2)

The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

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