WM8951L datasheet(23/42 Pages) WOLFSON

23 / 42 page

Production Data

WM8951

PD Rev 4.1 December 2007

Figure 19 Right Justified Mode

DSP mode is where the left channel MSB is available on either the 1st or 2nd rising edge of BCLK

(selectable by LRP) following a LRC transition high. Right channel data immediately follows left

channel data.

Figure 20 DSP Mode

In all modes ADCLRC must always change on the falling edge of BCLK, refer to Figure 17, Figure

18, Figure 19 and Figure 20.

Operating the digital audio interface in DSP mode allows ease of use for supporting the various

sample rates and word lengths. The only requirement is that all data is transferred within the correct

number of BCLK cycles to suit the chosen word length.

In order for the digital audio interface to offer similar support in the three other modes (Left Justified,

I2S and Right Justified), the ADCLRC and BCLK frequencies, continuity and mark-space ratios need

more careful consideration.

In Slave mode, ADCLRC is not required to have a 50:50 mark-space ratio. BCLK input need not be

continuous. It is however required that there are sufficient BCLK cycles for each ADCLRC transition

to clock the chosen data word length. The non-50:50 requirement on the LRC is of use in some

situations such as with a USB 12MHZ clock. Here simply dividing down a 12MHz clock within the

DSP to generate LRC and BCLK will not generate the appropriate ADCLRC since it will no longer

change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are 375 MCLK per

LRC. In these situations ADCLRC can be made non 50:50.

In Master mode, ADCLRC will be output with a 50:50 mark-space ratio with BCLK output at 64 x

base frequency (i.e. 48 kHz).

WM8951L bảng dữ liệu(PDF) 23 Page - Wolfson Microelectronics plc