PSD813F1 datasheet(37/120 Pages) STMICROELECTRONICS

37 / 120 page

Preliminary

PSD813F1-A

The

PSD813F1

Functional

Blocks

(cont.)

9.2 PLDs

The PLDs bring programmable logic functionality to the PSD813F1. After specifying the

logic for the PLDs using the PSDabel tool in PSDsoft, the logic is programmed into the

device and available upon power-up.

The PSD813F1 contains two PLDs: the Decode PLD (DPLD), and the Complex PLD

(CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in

sections 9.2.1 and 9.2.2. Figure 11 shows the configuration of the PLDs.

The DPLD performs address decoding for internal and external components, such as

memory, registers, and I/O port selects.

The CPLD can be used for logic functions, such as loadable counters and shift registers,

state machines, and encoding and decoding logic. These logic functions can be constructed

using the 16 Output Micro

⇔Cells (OMCs), 24 Input Micro⇔Cells (IMCs), and the AND

array. The CPLD can also be used to generate external chip selects.

The AND array is used to form product terms. These product terms are specified using

PSDabel. An Input Bus consisting of 73 signals is connected to the PLDs. The signals are

shown in Table 15.

Input Source

Input Name

Number

of Signals

MCU Address Bus

A[15:0]

MCU Control Signals

CNTL[2:0]

Reset

RST

Power Down

PDN

Port A Input Micro

⇔Cells

PA[7-0]

Port B Input Micro

⇔Cells

PB[7-0]

Port C Input Micro

⇔Cells

PC[7-0]

Port D Inputs

PD[2:0]

Page Register

PGR(7:0)

Micro

⇔Cell AB Feedback

MCELLAB.FB[7:0]

Micro

⇔Cell BC Feedback

MCELLBC.FB[7:0]

EEPROM Programming Status Bit

Rdy/Bsy

Table 15. DPLD and CPLD Inputs

NOTE: The address inputs are A[19:4] in 80C51XA mode.

The Turbo Bit in PSD813F1

The PLDs in the PSD813F1 can minimize power consumption by switching off when inputs

remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off

(Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs

are changing. Turbo-off mode increases propagation delays while reducing power

consumption. Refer to the Power Management Unit section on how to set the Turbo Bit.

Additionally, five bits are available in the PMMR2 register to block MCU control signals from

entering the PLDs. This reduces power consumption and can be used only when these

MCU control signals are not used in PLD logic equations.

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