PSD813F1 datasheet(18/120 Pages) STMICROELECTRONICS

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PSD813F1-A

Preliminary

Table 7 shows the offset addresses to the PSD813F1 registers relative to the CSIOP base

address. The CSIOP space is the 256 bytes of address that is allocated by the user to the

internal PSD813F1 registers. Table 7 provides brief descriptions of the registers in CSIOP

space. For a more detailed description, refer to section 9.

8.0

PSD813F1

Description

and Address

Offset

Port A Port B Port C Port D Other*

Description

Data In

Reads Port pin as input,

MCU I/O input mode

Control

Selects mode between

MCU I/O or Address Out

Stores data for output

Data Out

to Port pins, MCU I/O

output mode

Direction

Configures Port pin as

input or output

Configures Port pins as

either CMOS or Open

Drive Select

Drain on some pins, while

selecting high slew rate

on other pins.

Input Micro

⇔Cell

Reads Input Micro

⇔Cells

Reads the status of the

Enable Out

output enable to the I/O

Port driver

Read – reads output of

Output

Micro

⇔Cells AB

Micro

⇔Cells AB

Write – loads Micro

⇔cell

Flip-Flops

Read – reads output of

Output

Micro

⇔Cells BC

Micro

⇔Cells BC

Write – loads Micro

⇔cell

Flip-Flops

Mask

Blocks writing to the

Micro

⇔Cells AB

Output Micro

⇔Cells AB

Mask

Blocks writing to the

Micro

⇔Cells BC

Output Micro

⇔Cells BC

Flash Protection

Read only – Flash Sector

Protection

PSD/EE

Read only – PSD Security

Protection

and EEPROM Sector

Protection

JTAG Enable

Enables JTAG Port

PMMR0

Power Management

PMMR2

Power Management

Page

Page Register

Places PSD memory

areas in Program and/or

Data space on an

individual basis.

Table 7. Register Address Offset

*Other registers that are not part of the I/O ports.

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