PSD813F1 datasheet(36/120 Pages) STMICROELECTRONICS

tên linh kiện	PSD813F1

Giải thích chi tiết về linh kiện	Flash In-System Programmable ISP Peripherals For 8-bit MCUs

PDF	120 Pages

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nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

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PSD813F1-A

Preliminary

RESET

D 0-D 7

R/W

PAGE

PGR0

PGR1

PGR2

PGR3

FLASH

DPLD

AND

FLASH

CPLD

INTERNAL

SELECTS

AND LOGIC

FLASH

PLD

PGR4

PGR5

PGR6

PGR7

Figure 10. Page Register

The

PSD813F1

Functional

Blocks

(cont.)

9.1.4 Page Register

The eight bit Page Register increases the addressing capability of the microcontroller by a

factor of up to 256. The contents of the register can also be read by the microcontroller. The

outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be

included in the Flash Memory, EEPROM, and SRAM chip select equations.

If memory paging is not needed, or if not all 8 page register bits are needed for memory

paging, then these bits may be used in the CPLD for general logic. See Application

Note 57.

Figure 10 shows the Page Register. The eight flip flops in the register are connected to the

internal data bus D0-D7. The microcontroller can write to or read from the Page Register.

The Page Register can be accessed at address location CSIOP + E0h.

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