7.3.3 WDO Output

The TPS3435-Q1 device offers WDO output pin. WDO output is asserted when MR pin voltage is lower than 0.3

X VDD or watchdog timer error is detected.

The output is asserted for tWDO time when any relevant events described above are detected, except for MR

event. The time tWDO can be programmed by connecting a capacitor between CRST pin and GND or the

device asserts tWDO for fixed time duration as selected by orderable part number. Refer Section 4 section for all

available options.

Equation 2 describes the relationship between capacitor value and the time tWDO . Make sure the capacitance

meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect

operation of the device.

t WDO (sec) = 4.95 x 106 x CCRST (F)

(2)

TPS3435-Q1 also offers a unique option of latched output. An orderable with latched output holds the output in

asserted state indefinitely until the device is power cycled or the error condition is addressed. If the output is

latched due to MR pin low voltage, the output latch is released when MR pin voltage rises above 0.7 x VDD level.

If the output is latched due to watchdog timer error, the output latch is be released when a WDI negative edge is

detected or the device is shutdown and powered up again. Figure 7-11 shows timing behavior of the device with

latched output configuration.

WDO

WDI

tt

WDt

tt

WDt

VDD

VDD

MIN

tt

SDt

t

WD

tt

SDt

V

POR

t

STRT

Figure 7-11. Output Latch Timing Behavior

TPS3435-Q1

SLVSGF0B – OCTOBER 2022 – REVISED MARCH 2025

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