7.3.1.3 tSD Watchdog Start Up Delay

The TPS3435-Q1 supports watchdog startup delay feature. This feature is activated after power up or after WDO

assert event. When tSD frame is active, the device monitors the WDI pin but the WDO output is not asserted.

This feature allows time for the host complete boot process before watchdog monitoring can take over. The start

up delay helps avoid unexpected WDO assert events during boot. The tSD time is predetermined based on the

device part number selected. Refer Section 4 section for details to map the part number to tSD time. Pinout

option A, B are available only in no delay or 10 sec start up delay options.

To exit tSD frame, one of the following event must occur:

• The host provides a valid pulse transition on the WDI pin.

• Change in logic state of SET[1:0].

• Toggling of the WD_EN pin.

The device enters watchdog monitoring phase after the device exits the tSD frame.

Failure to provide one of the exit condition within tSD triggers the watchdog error by asserting the WDO output

pin for tD, this is observed in Figure 7-6.

The tSD frame is not initiated when the watchdog functionality is enabled using WD-EN pin or SET[1:0] pin

combination as described in Section 7.3.1.2 section.

Figure 7-6 shows the operation for tSD time frame.

VDD

WDI

Ignore

ttSDt

ttWDOt

VPOR

ttWDt

ttWDt

ttSDt

Ignore

tSTRT

WDO

VDDMIN

Figure 7-6. tSD Frame Behavior

7.3.1.4 SET Pin Behavior

The TPS3435-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the

user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET

pin can be used are:

• Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is

operational. Watchdog can be used to wake up the host after long duration to perform the application related

activities before going back to sleep.

• Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not

interrupt the critical task. Change timer to application specified interval after the critical task is complete.

The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value

along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in

the Section 4 section. The SET pin logic level is decoded during the device power up. The SET pin value can

be changed any time during the operation. SETx pin change which leads to change of watchdog timer value

or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when

TPS3435-Q1

SLVSGF0B – OCTOBER 2022 – REVISED MARCH 2025

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