R7KA8M2AFDCAC datasheet(166/295 Pages) RENESAS

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Table 2.63

SPI timing (3 of 5)

Conditions:

1. High-speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:

RSPCLKA_B, RSPCLKB_B.

For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

2. Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership.

3. Load capacitance C = 15pF is applied to the VCC/VCC2 condition “3.00 V or above”.

Parameter

High Speed/

Default

VCC/VCC2

Symbol

Min

Max

Unit

Note

Data input

setup time

Master

—

3.00 V or above

tSU

−2.5

—

Figure 2.76,

Figure 2.77

—

2.70 V or above

0.0

—

1.62 V or above

0.0

—

Slave

High Speed*1 3.00 V or above

1.5

—

High Speed*1 2.70 V or above

1.5

—

High Speed*1 1.62 V or above

1.5

—

Default*2

3.00 V or above

2.5

—

Default*2

2.70 V or above

2.5

—

Default*2

1.62 V or above

2.5

—

Data input

hold time

Master

—

3.00 V or above

7.5

—

2.70 V or above

7.5

—

1.62 V or above

9.5

—

Slave

High Speed*1 3.00 V or above

1.5

—

High Speed*1 2.70 V or above

1.5

—

High Speed*1 1.62 V or above

1.5

—

Default*2

3.00 V or above

2.5

—

Default*2

2.70 V or above

2.5

—

Default*2

1.62 V or above

5.5

—

SSL setup

time

Master

—

3.00 V or above

tLEAD

1 × tSPcyc − 10

8 × tSPcyc

+ 10

Figure 2.76,

Figure 2.77

—

2.70 V or above

1 × tSPcyc − 10

8 × tSPcyc

+ 10

—

1.62 V or above

1 × tSPcyc − 10

8 × tSPcyc

+ 10

Slave

—

3.00 V or above

5.0

—

tTcyc

—

2.70 V or above

5.0

—

1.62 V or above

5.0

—

SSL hold

time

Master

—

3.00 V or above

tLAG

1 × tSPcyc − 10

8 × tSPcyc

+ 10

—

2.70 V or above

1 × tSPcyc − 10

8 × tSPcyc

+ 10

—

1.62 V or above

1 × tSPcyc−- 10

8 × tSPcyc

+ 10

Slave

—

3.00 V or above

5.0

—

tTcyc

—

2.70 V or above

5.0

—

1.62 V or above

5.0

—

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 166 of 295

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