R7KA8M2AFDCAC datasheet(84/295 Pages) RENESAS

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Table 2.35

Coremark and normal mode current, CPU0 Deep Sleep, CPU1 active. (DCDC mode and External VDD

mode) (2 of 2)

Parameter

Symbol Typ

Max

Uni

Test conditions

95 °C 105

°C

125

°C

Supply

current*1

CPUCLK1 =

200 MHz

VSCR_1

VCL =

voltage

range 1

Coremark

Cache on

IDD

226 —

—

μA/

CPU0 = Deep Sleep

ESWM power domain off

CPUCLK0 = 600 MHz,

MRICLK = 200 MHz, MRPCLK

= 25 MHz, ICLK = 200 MHz,

PCLKA = 25 MHz, PCLKB =

25 MHz, PCLKC = 25 MHz,

PCLKD = 25 MHz, PCLKE =

25 MHz, BCLK = 25MHz

Cache off,

executing from

ITCM

208 —

—

Cache off,

executing from

SRAM

205 —

—

Cache off,

executing from

MRAM

289 —

—

Normal

mode

All peripheral

disabled, Cache

on, while (1) code

213 —

—

All peripheral

disabled, Cache

off, while (1) code

executing from

MRAM

287 —

—

CPUCLK1 =

150 MHz

VSCR_2

VCL =

voltage

range 2

Coremark

Cache on

265 —

—

μA/

CPU0 = Deep Sleep

ESWM power domain off

CPUCLK0 = 600 MHz,

MRICLK = 150 MHz, MRPCLK

= 9.4 MHz, ICLK = 150 MHz,

PCLKA = 9.4 MHz, PCLKB =

9.4 MHz, PCLKC = 9.4 MHz,

PCLKD = 9.4 MHz, PCLKE =

9.4 MHz, BCLK = 9.4 MHz

Cache off,

executing from

ITCM

247 —

—

Cache off,

executing from

SRAM

244 —

—

Cache off,

executing from

MRAM

326 —

—

Normal

mode

All peripheral

disabled, Cache

on, while (1) code

252 —

—

All peripheral

disabled, Cache

off, while (1) code

executing from

MRAM

324 —

—

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 84 of 295

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