R7KA8M2AFDCAC datasheet(59/295 Pages) RENESAS

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Table 2.10

Current of high-speed mode, maximum condition (MVE and peripheral operation), CPU0 active, CPU1

Deep Sleep (DCDC mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C 125 °C

Supply

current

*1*2*5

—

ICC

3.85

6.27

6.69

8.01

—

CPUC

LK0 =

1 GHz

CPUC

LK1 =

250

MHz

VSCR_

VCC_DCD

C ≥ 2.5V

ICC_DCDC *4 168

329

—

VCC_DCDC = 3.3 V

MRICLK = 250 MHz, MRPCLK = 125 MHz,

ICLK = 250 MHz, BCLK = 125 MHz, PCLKA

= 125 MHz, PCLKB = 62.5 MHz, PCLKC =

125 MHz, PCLKD = 250 MHz, PCLKE = 250

MHz

CPU1 = Deep Sleep

IDD *3

430

844

—

VCC_DCD

C < 2.5V

ICC_DCDC *4 327

642

—

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

430

844

—

CPUC

LK0 =

800

MHz

CPUC

LK1 =

200

MHz

VSCR_

VCC_DCD

C ≥ 2.5V

ICC_DCDC *4 141

—

347

—

VCC_DCDC = 3.3 V

MRICLK = 200 MHz, MRPCLK = 100 MHz,

ICLK = 200 MHz, BCLK = 100 MHz, PCLKA

= 100MHz, PCLKB = 50 MHz, PCLKC =

100 MHz, PCLKD = 200 MHz, PCLKE = 200

MHz

CPU1 = Deep Sleep

IDD *3

362

—

891

—

VCC_DCD

C < 2.5V

ICC_DCDC *4 275

—

678

—

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

362

—

891

—

CPUC

LK0 =

600

MHz

CPUC

LK1 =

200

MHz

VSCR_

VCC_DCD

C ≥ 2.5V

ICC_DCDC *4 122

—

380

VCC_DCDC = 3.3 V

MRICLK = 200 MHz, MRPCLK = 100 MHz,

ICLK = 200 MHz, BCLK = 100 MHz, PCLKA

= 100 MHz, PCLKB = 50 MHz, PCLKC =

100 MHz, PCLKD = 200 MHz, PCLKE = 200

MHz

CPU1 = Deep Sleep

IDD *3

312

—

976

VCC_DCD

C < 2.5V

ICC_DCDC *4 237

—

742

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

312

—

976

CPUC

LK0 =

600

MHz

CPUC

LK1 =

150

MHz

VSCR_

VCC_DCD

C ≥ 2.5V

ICC_DCDC *4 110

274

301

359

VCC_DCDC = 3.3 V

MRICLK = 150 MHz, MRPCLK = 75 MHz,

ICLK = 150 MHz, BCLK = 75 MHz, PCLKA

= 75 MHz, PCLKB = 37.5 MHz, PCLKC =

75 MHz, PCLKD = 150 MHz, PCLKE = 150

MHz

CPU1 = Deep Sleep

IDD *3

289

718

788

940

VCC_DCD

C < 2.5V

ICC_DCDC *4 216

536

588

701

VCC_DCDC = 1.8 V

Clock settings are the same as above

IDD

289

718

788

940

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Measured with clocks supplied to the peripheral functions and peripherals being operated. This does not include the BGO

operation.

Note 3. IDD depends on f (CPUCLK0 and ICLK) as follows.

IDD Typ. = 0.25 × fCPUCLK0 + 0.71 × fICLK + 21 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 95℃) = 0.22 × fCPUCLK0 + 0.70 × fICLK + 474 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 105℃) = 0.22 × fCPUCLK0 + 0.70 × fICLK + 549 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 125℃) = 0.22 × fCPUCLK0 + 0.70 × fICLK + 704 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 95℃) = 0.22 × fCPUCLK0 + 0.83 × fICLK + 461 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 105℃) = 0.22 × fCPUCLK0 + 0.83 × fICLK + 533 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 125℃) = 0.22 × fCPUCLK0 + 0.83 × fICLK + 686 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 4. Typical DCDC efficiency and the voltage of the test conditions are applied.

Note 5. The power consumption is calculated as Power = VCC × Icc + VCC_DCDC × Icc_DCDC.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 59 of 295

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