R7KA8M2AFDCAC datasheet(165/295 Pages) RENESAS

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Table 2.63

SPI timing (2 of 5)

Conditions:

1. High-speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:

RSPCLKA_B, RSPCLKB_B.

For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

2. Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership.

3. Load capacitance C = 15pF is applied to the VCC/VCC2 condition “3.00 V or above”.

Parameter

High Speed/

Default

VCC/VCC2

Symbol

Min

Max

Unit

Note

RSPCK clock

high pulse

width

Master

—

3.00 V or above

tSPCKWH (tSPcyc – tSPCKr – tSPCKf) / 2 –

—

Figure 2.75

—

2.70 V or above

(tSPcyc – tSPCKr – tSPCKf) / 2 –

—

1.62 V or above

(tSPcyc – tSPCKr – tSPCKf) / 2 –

—

Slave

—

1.62 V or above

0.4

—

tSPcyc

RSPCK clock

low pulse

width

Master

—

3.00 V or above

tSPCKWL (tSPcyc – tSPCKr – tSPCKf) / 2 –

—

2.70 V or above

(tSPcyc – tSPCKr – tSPCKf) / 2 –

—

1.62 V or above

(tSPcyc – tSPCKr – tSPCKf) / 2 –

—

Slave

—

1.62 V or above

0.4

—

tSPcyc

RSPCK clock

rise and fall

time

Output

High Speed*1 3.00 V or above

tSPCKr,

tSPCKf

—

0.80

High Speed*1 2.70 V or above

—

1.40

High Speed*1 1.62 V or above

—

2.50

Default*2

3.00 V or above

—

1.66

Default*2

2.70 V or above

—

3.30

Default*2

1.62 V or above

—

6.60

Input

—

3.00 V or above

—

0.1*3

µs

—

2.70 V or above

—

0.1*3

—

1.62 V or above

—

0.1*3

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 165 of 295

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