R7KA8M2AFDCAC datasheet(164/295 Pages) RENESAS

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2.3.10

SPI Timing

Table 2.63

SPI timing (1 of 5)

Conditions:

1. High-speed high drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins:

RSPCLKA_B, RSPCLKB_B.

For other pins, high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

2. Use pins that have a letter appended to their names, for instance “_A” or “_B” to indicate group membership.

3. Load capacitance C = 15pF is applied to the VCC/VCC2 condition “3.00 V or above”.

Parameter

High Speed/

Default

VCC/VCC2

Symbol

Min

Max

Unit

Note

RSPCK clock

cycle

Master

High Speed*1 3.00 V or above

tSPcyc

4096

tTcyc

Figure 2.75

High Speed*1 2.70 V or above

2 (TCLK ≤ 166.6MHz)

4 (TCLK > 166.6 MHz)

4096

High Speed*1 1.62 V or above

2 (TCLK ≤ 83.3MHz)

4 (TCLK ≤ 166.6 MHz)

8 (TCLK > 166.6 MHz)

4096

Default*2

3.00 V or above

2 (TCLK ≤ 166.6 MHz)

4 (TCLK > 166.6 MHz)

4096

Default*2

2.70 V or above

2 (TCLK ≤ 120MHz)

4 (TCLK ≤ 240 MHz)

8 (TCLK > 240 MHz)

4096

Default*2

1.62 V or above

2 (TCLK ≤ 60 MHz)

4 (TCLK ≤ 120 MHz)

8 (TCLK ≤ 240 MHz)

16 (TCLK > 240 MHz)

4096

Slave

High Speed*1 3.00 V or above

2 (TCLK ≤ 266 MHz)

4 (TCLK > 266 MHz)

—

High Speed*1 2.70 V or above

2 (TCLK ≤ 166.6 MHz)

4 (TCLK > 166.6 MHz)

—

High Speed*1 1.62 V or above

2 (TCLK ≤ 83.3MHz)

4 (TCLK ≤ 166.6 MHz)

8 (TCLK > 166.6 MHz)

—

Default*2

3.00 V or above

2 (TCLK ≤ 166.6 MHz)

4 (TCLK > 166.6 MHz)

—

Default*2

2.70 V or above

2 (TCLK ≤ 120 MHz)

4 (TCLK ≤ 240 MHz)

8 (TCLK > 240 MHz)

—

Default*2

1.62 V or above

2 (TCLK ≤ 60 MHz)

4 (TCLK ≤ 120 MHz)

8 (TCLK ≤ 240 MHz)

16 (TCLK > 240 MHz)

—

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 164 of 295

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