R7KA8M2AFDCAC datasheet(149/295 Pages) RENESAS

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Table 2.57

I/O ports, POEG, GPT, AGT, ULPT and ADC trigger timing (4 of 4)

GPT32 Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If GPT pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

AGT Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

AGT

AGTIO, AGTEE input cycle

2.70 V or

above

tACYC*2

100

—

Figure 2.65

1.62 V or

above

100

—

AGTIO, AGTEE input high width, low

width

2.70 V or

above

tACKWH,

tACKWL

—

1.62 V or

above

—

AGTIO, AGTO, AGTOA, AGTOB output

cycle

2.70 V or

above

tACYC2

62.5

—

1.62 V or

above

62.5

—

ULPT

ULPTEE, ULPTEVI input cycle

2.70 V or

above

tULCYC*3

—

µs

Figure 2.66

1.62 V or

above

—

ULPTEE, ULPTVI input high width, low

width

2.70 V or

above

tULCKWH,

tULCKWL

—

µs

1.62 V or

above

—

ULPTO, ULPTOA, ULPTOB output cycle 2.70 V or

above

tULCYC2

—

µs

1.62 V or

above

—

ADC

ADC trigger input pulse width

2.70 V or

above

tTRGW

1.5

—

tADcyc

Figure 2.67

1.62 V or

above

3.0

—

Note:

tIcyc: ICLK cycle, tPcyc: PCLKB cycle, tPDcyc: GTCLK cycle, tULPTLCLK: ULPTLCLK cycle, tADcyc: ADCLK cycle.

Note 1. For Cycle and Time, the longer time characteristics are applied.

Note 2. Constraints on input cycle:

When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.

When switching the source clock: tPcyc × 6 < tACYC should be satisfied.

Note 3. Constraints on input cycle:

ULPTEVI: tPcyc × 2 < tULCYC should be satisfied.

ULPTEE: tULPTLCLK × 2 < tULCYC should be satisfied.

Port

tPRW

Figure 2.52

I/O ports input timing

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

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