R7KA8M2AFDCAC datasheet(147/295 Pages) RENESAS

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Table 2.57

I/O ports, POEG, GPT, AGT, ULPT and ADC trigger timing (2 of 4)

GPT32 Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If GPT pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

AGT Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

POEG

POEG input trigger pulse width

tPOEW

—

tPcyc

Figure 2.54

Output disable time

Input level

detection of

the GTETRGn

pin (via flag)

tPOEGDI

—

PCLK

B +

0.34

µs

Figure 2.55

When the digital

noise filter is

not in use

(POEGGn.NFEN = 0

(n = A to D))

Detection of

the output

stopping signal

from GPT

(deadtime

error,

simultaneous

high output, or

simultaneous

low output)

tPOEGDE

—

0.5

µs

Figure 2.56

Edge detection

signal from a

comparator

tPOEGDC

—

PCLK

B +

0.5

µs

Figure 2.57

The time is that

when the noise

filter for ACMPHS

is not in use

(CMPCTL.CDFS

[1:0] = 00b) and

excludes the time

for detection by

ACMPHS.

setting

tPOEGDS

—

0.3

µs

Figure 2.58

Time for access to

the register is not

included.

Oscillation stop

detection

tPOEGDOS —

1.3

µs

Figure 2.59

Level detection

signal from a

comparator

tPOEGDDC —

0.5

µs

Figure 2.60

The time is that

when the noise

filter for ACMPHS

is not in use

(CMPCTL.CDFS

[1:0] = 00b) and

excludes the time

for detection by

ACMPHS.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 147 of 295

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