R7KA8M2AFDCAC datasheet(148/295 Pages) RENESAS

148 / 295 page

Table 2.57

I/O ports, POEG, GPT, AGT, ULPT and ADC trigger timing (3 of 4)

GPT32 Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If GPT pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

AGT Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

GPT

Input capture pulse width (Cycle)

Single edge

tGTICW*1

1.5

—

tPDcyc

Figure 2.61

Dual edge

2.5

—

Input capture pulse width (Times)

2.70 V or

above

tGTICW*1

8.3

—

1.62 V or

above

10.0

—

GTIOCxY output skew

(x = 0 to 3, Y = A or B)

Middle drive

output

2.70 V or

above

tGTISK

—

Figure 2.62

1.62 V or

above

—

High drive

output

2.70 V or

above

3.5

1.62 V or

above

4.5

GTIOCxY output skew

(x = 4 to 13, Y = A or B)

Middle drive

output

2.70 V or

above

—

1.62 V or

above

—

High drive

output

2.70 V or

above

—

3.5

1.62 V or

above

—

4.5

GTIOCxY output skew

(x = 0 to 13, Y = A or B)

Middle drive

output

2.70 V or

above

—

1.62 V or

above

—

High drive

output

2.70 V or

above

—

3.5

1.62 V or

above

—

OPS output skew

GTOUUP, GTOULO,

GTOVUP, GTOVLO,

GTOWUP, GTOWLO

Middle drive

output

2.70 V or

above

tGTOSK

—

Figure 2.63

1.62 V or

above

—

GPT (PWM

Delay

Generation

Circuit)

GTIOCxY output skew

(x = 0 to 3, Y = A or B)

Middle drive

output

2.70 V or

above

tHRSK

—

Figure 2.64

1.62 V or

above

—

High drive

output

2.70 V or

above

—

3.5

1.62 V or

above

—

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 148 of 295

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