R7FA6T2AB3CFL datasheet(39/101 Pages) RENESAS

39 / 101 page

Table 2.20

I/O ports, POEG, GPT, AGT, KINT and ADC trigger timing (4 of 4)

GPT Conditions:

High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

AGT Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

ADC

ADC trigger input pulse width

tTRGW

1.5

—

tADcyc

Figure 2.31

Note:

tIcyc: ICLK cycle, tPcyc: PCLKB cycle, tPDcyc: GTCLK cycle, tADcyc: ADCLK cycle.

Note 1. This skew applies when the same driver I/O is used. If the I/O of the middle and high drivers is mixed, operation is not guaranteed.

Note 2. Constraints on input cycle:

When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.

When switching the source clock: tPcyc × 6 < tACYC should be satisfied.

Note 3. Reference value.

Port

tPRW

Figure 2.14

I/O ports input timing

GTETRGn input

(n = A to D)

tPOEW

Figure 2.15

POEG input trigger timing

GTETRGn input

(n = A to D)

GPT output pins

Outputs disabled

tPOEGDI

tPOEGW

POEGGn.PIDF flag

(n = A to D)

Figure 2.16

Output Disable Time for POEG via Detection Flag in Response to the Input Level Detection of

the GTETRGn pin

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0150 Rev.1.50

Jul 2, 2025

Page 39 of 101

R7FA6T2AB3CFL bảng dữ liệu(PDF) 39 Page - Renesas Technology Corp

R7FA6T2AB3CFL bảng dữ liệu(HTML) 39 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL