ams.com

db09284e_V3.01_preliminary_2017-07-06

Page 20 of 30

AS89020

V3.01

CREG

NAME

VALUE [B]

DESCRIPTION

19

input current direction is into the inputs INX – common

cathode photodiodes (see Figure 15 (a))

09

the falling edge of the signal CSN captures the sample

of the input signals at all INX

1

the falling edge of the signal CONVN captures the

sample of the input signals at all INX

09

set for a supply voltage > 2.9 V

1

set for a supply voltage <= 2.9 V

bit 2-0

00010

reserved; these bits must be set to ,000b’ otherwise the

operation of the AS89020 fails

For better understanding of the proper use of CREG:TCOMPENA please see chapter 5.7.

The bit CREG:OFFGEN enables an internal offset generation for the input currents of all INX and for their

conversion results. It helps to measure very low (e.g. zero) input currents even in presence of a negative

leakage current at the inputs INX, which would normally lead to an underflow. The conversion result under

ideal conditions (no device offsets and no leakage currents) would lead to a decimal value of 63 (,3Fh’).

This must be considered for the conversion result under real conditions.

The bit CREG:DIR must be set depending on which direction the input current flows of all inputs INX.

For the proper use of the bit CREG:STARTSIG please see chapter 6.4 .

The bit CREG:SETVB is very important to concerning the power supply range of the AS89020, which is

used.

6.5 Transimpedance Register – SW_RX

The transimpedance of each channel can be chosen by setting the register SW_RX, where X stands for the

channel number 0…3, so every channel comes with its own register. The bits SW_RX[3:0] support a binary

subdivision of the transimpedance for each channel. Using additional bit SW_RX[4] some intermediate

stages of a few more transimpedance values can be chosen.

The bit SW_RX[5] is for a special purpose. If SW_RX[5] is set to ‘1b’, the input of the transimpedance

amplifier will disconnected from the appropriate input pin (IN[x]).

So the leftover offset of the internal

chip could be measured. The offset value depends on the settings for the transimpedance defined by

SW_RX[4:].

During the configuration of the transimpedance via SPI the leading bits SW_RX[7:6] should be ,00b’.

Table 11: Registers SW_RX (X = 0…3) – Addresses 07h, 08h, 09h and 0Ah

STAGE

SW_RX[4]

[B]

SW_RX[3:0]

[HEX]

TRANSIMPEDANCE

[MΩ]

ADC REFERENCE CURRENT (FSR)

0

0

0

0.1

12 µA

6·21 µA

110

0

1

0.2

6 µA

6·20 µA

2

0

2

0.4

3 µA

6·2–1 µA

3

0

3

0.8

1.5 µA

6·2–2 µA

4

0

4

1.6

750 nA

6·2–3 µA

10 Default after power-on-reset.