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db09284e_V3.01_preliminary_2017-07-06

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AS89020

V3.01

STAGE

SW_RX[4]

[B]

SW_RX[3:0]

[HEX]

TRANSIMPEDANCE

[MΩ]

ADC REFERENCE CURRENT (FSR)

5

0

5

3.2

375 nA

6·2–4 µA

6

0

6

6.4

187.5 nA

6·2–5 µA

7

0

7

12.8

93.75 nA

6·2–6 µA

8

0

8

25.6

46.875 nA

6·2–7 µA

9

0

9

51.2

23.4375 nA

6·2–8 µA

10-15

0

A, B, C, D, E, F

102.4

11.71875 nA

6·2–9 µA

16-20

1

0, 1, 2, 3, 4

2.4

500 nA

4·2–3 µA

21

1

5

4.8

250 nA

4·2–4 µA

22

1

6

9.6

125 nA

4·2–5 µA

23

1

7

19.2

62.5 nA

4·2–6 µA

24

1

8

38.4

31.25 nA

4·2–7 µA

25-31

1

9, A, B, C, D, E,

F

76.8

15.625 nA

4·2–8 µA

6.6 Channel Power Down Register – CH_PD

The Power Down setting for each transimpedance amplifier channel separately or their combination can be

programmed in register CH_PD as shown in Table 12. It is valid as long as the bit OSR:PD = ,0b’ and the

pin PDN = VDD.

A Power Down for the whole device can be activated by setting bit OSR:PD to ,1b’ or PDN = VDD, which

overrides the channel Power Down settings via register CH_PD (see also chapter 5.3).

Table 12: Register CH_PD – Address 0Bh

CH_PD

NAME

VALUE [B]

DESCRIPTION

bit 7 to 4

000011

reserved

000011

all channels active

XXX1

Power Down mode for channel 0

XX1X

Power Down mode for channel 1

X1XX

Power Down mode for channel 2

1XXX

Power Down mode for channel 3

11 Default after power-on-reset