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db09284e_V3.01_preliminary_2017-07-06

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AS89020

V3.01

6.7 Channel Order Register – CH_ORDER

The conversion and read out order of the four channels after every sampling can be programmed freely by

register CH_ORDER. Every channel address must be present one time.

Table 13: Register CH_ORDER – Address 0Ch

CH_ORDER

Name

Value [b]

Description

bit 7-6

1st

xx

address of channel to be converted and read 1st (default 00)

bit 5-4

2nd

xx

address of channel to be converted and read 2nd (default 01)

bit 3-2

3rd

xx

address of channel to be converted and read 3rd (default 10)

bit 1-0

4th

xx

address of channel to be converted and read 4th (default 11)

As an example for an order to read out channel 3, 2, 0 and 1 register CH_ORDER has to be set with the

value ,11100001b’.

6.8 Channel Output Data Format

The channel conversion result is always 2 bytes long and contains some status information (4 MSB) and

the 12 bit value of the ADC (see Table 14).

Table 14: Channel Output Data Format

Channel (Output) Data

Name

Description

bit 15–14

CHANNEL

return of channel address (,00b’ for IN0 until ,11b’ for

IN3)

bit 13

STARTSIG

shows the actually used sample signal

returns ,0’ for CSN and ,1’ for CONVN

bit 12

TR_ON

active only if STARTSIG = ,1’

returns a ,1’ if the CONVN sample signal came before

the start of conversion by CSN

bit 11–0

ADC

12 bit result of the AD conversion (bit 11 = MSB)