RA4L1 datasheet(61/125 Pages) RENESAS

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SDAn

SCLn

VIH

VIL

P*1

S*1

tSf

tSr

tSDAH

tSDAS

tSP

P*1

Test conditions:

VIH = VCC × 0.7, VIL = VCC × 0.3

VOL = 0.6 V, IOL = 6 mA

Sr*1

Note:

n = 0, 1, 3 to 5, 9

Note 1. S, P, and Sr indicate the following conditions:

S: Start condition

P: Stop condition

Sr: Restart condition

Figure 2.30

SCI simple IIC mode timing

2.3.9

SPI Timing

Table 2.39

SPI timing (1 of 3)

Parameter

Symbol

Min

Max

Unit

Test conditions

RSPCK clock

cycle

Master

2.7 V ≤ VCC ≤ 3.6 V

tSPcyc*1

—

Figure 2.31

C = 30 pF

2.4 V ≤ VCC < 2.7 V

100

—

1.8 V ≤ VCC < 2.4 V

200

—

1.6 V ≤ VCC < 1.8 V

500

—

Slave

2.7 V ≤ VCC ≤ 3.6 V

100

—

2.4 V ≤ VCC < 2.7 V

200

—

1.8 V ≤ VCC < 2.4 V

400

—

1.6 V ≤ VCC < 1.8 V

1500

—

RSPCK clock

high pulse width

Master

tSPCKWH

(tSPcyc – tSPCKr –

tSPCKf) / 2 – 3

—

Slave

0.4 × tSPcyc

0.6 × tSPcyc

RSPCK clock

low pulse width

Master

tSPCKWL

(tSPcyc – tSPCKr –

tSPCKf) / 2 – 3

—

Slave

0.4 × tSPcyc

0.6 × tSPcyc

RSPCK clock

rise and fall time

Output

2.7 V ≤ VCC ≤ 3.6 V

tSPCKr,

tSPCKf

—

2.4 V ≤ VCC < 2.7 V

—

1.8 V ≤ VCC ≤ 2.4 V

—

1.6 V ≤ VCC < 1.8 V

—

Input

—

µs

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

Page 61 of 125

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