RA4L1 datasheet(49/125 Pages) RENESAS

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2.3.4

Wakeup Time

Table 2.28

Timing of recovery from low power modes (1)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Recovery time

from Software

Standby

mode*1

High-speed

mode

Crystal

resonator

connected to

main clock

oscillator

System clock source is

main clock oscillator (20

MHz)*2 *4

tSBYMC

—

2.1

2.7

Figure 2.14

System clock source is

PLL (48 MHz) with Main

clock oscillator*2 *5

tSBYPC

—

2.1

2.8

External clock

input to main

clock oscillator

System clock source is

main clock oscillator (20

MHz)*3 *4

tSBYEX

—

8.5

µs

System clock source is

PLL (48 MHz) with Main

clock oscillator*3 *5

tSBYEX

—

µs

System clock source is HOCO (HOCO

clock is 32 MHz)*6

tSBYHO

—

13.5

17.8

µs

System clock source is HOCO (HOCO

clock is 48 MHz)*5

tSBYHO

—

13.2

17.5

µs

System clock source is MOCO (8 MHz)*7

tSBYMO

—

3.5

5.1

µs

Note 1. The division ratio of ICLK, FCLK, and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time

is determined by the system clock source.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.

Note 4. The ICLK is 20 MHz

Note 5. The ICLK is 48 MHz

Note 6. The ICLK is 32 MHz

Note 7. The ICLK is 8 MHz

Table 2.29

Timing of recovery from low power modes (2)

Parameter

Symbol

Min Typ

Max

Unit

Test conditions

Recovery

time from

Software

Standby

mode*1

Middle

speed

mode

Crystal resonator

connected to main

clock oscillator

System clock source is

main clock oscillator (20

MHz)*2 *4

tSBYMC

—

2.1

2.7

Figure 2.14

External clock input

to main clock

oscillator

System clock source is

main clock oscillator (20

MHz)*3 *4

VCC = 1.8 V to 3.6 V

tSBYEX

—

7.4

µs

System clock source is

main clock oscillator (4

MHz)*3 *5

VCC = 1.6 V to 1.8 V

—

7.3

8.8

µs

System clock

source is HOCO

(32 MHz) *4

VCC = 1.8 V to 3.6 V*6

tSBYHO

—

µs

VCC = 1.6 V to 1.8 V*7

—

System clock

source is MOCO (8

MHz)

VCC = 1.8 V to 3.6 V*8

tSBYMO

—

3.5

5.1

µs

VCC = 1.6 V to 1.8 V*9

—

6.3

8.7

Note 1. The division ratio of ICLK, FCLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time

is determined by the system clock source.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.

Note 4. The ICLK is 5 MHz (20 MHz/4)

Note 5. The ICLK is 4 MHz

Note 6. The ICLK is 8 MHz (32 MHz/4)

Note 7. The ICLK is 4 MHz (32 MHz/8)

Note 8. The ICLK is 8 MHz

Note 9. The ICLK is 4 MHz (8 MHz/2)

RA4L1 Datasheet

2. Electrical Characteristics

R01DS0447EJ0131 Rev.1.31

May 26, 2026

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