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Table 2.30

IIC timing (2)

Setting of the SCL0_A, SDA0_A pins is not required with the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

IIC

(Fast-mode+)

ICFER.FMPE = 1

SCL input cycle time

tSCL

6 (12) × tIICcyc +

240

—

Figure 2.42

SCL input high pulse width

tSCLH

3 (6) × tIICcyc + 120 —

SCL input low pulse width

tSCLL

3 (6) × tIICcyc + 120 —

SCL, SDA rise time

tSr

—

120

SCL, SDA fall time

tSf

20 × (external

pullup voltage/

5.5V)

120

SCL, SDA input spike pulse

removal time

tSP

1 (4) × tIICcyc

SDA input bus free time when

wakeup function is disabled

tBUF

3 (6) × tIICcyc + 120 —

SDA input bus free time when

wakeup function is enabled

tBUF

3 (6) × tIICcyc + 4 ×

tPcyc + 120

—

Start condition input hold time

when wakeup function is disabled

tSTAH

tIICcyc + 120

—

START condition input hold time

when wakeup function is enabled

tSTAH

1 (5) × tIICcyc +

tPcyc + 120

—

Restart condition input setup time

tSTAS

120

—

Stop condition input setup time

tSTOS

120

—

Data input setup time

tSDAS

tIICcyc + 30

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*1

—

550

Note:

tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.

Note:

Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1.

Note 1. Cb indicates the total capacity of the bus line.

RA4E1 Datasheet

2. Electrical Characteristics

R01DS0391EJ0130 Rev.1.30

Jun 6, 2025

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