RA4E1 datasheet(45/81 Pages) RENESAS

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2.3.9

SPI Timing

Table 2.27

SPI timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

SPI

RSPCK clock cycle

Master

tSPcyc

4096

tPcyc

Figure 2.33

Slave

4096

RSPCK clock high

pulse width

Master

tSPCKWH

(tSPcyc – tSPCKr – tSPCKf) /

2 – 3

—

Slave

0.4

0.6

tSPcyc

RSPCK clock low

pulse width

Master

tSPCKWL

(tSPcyc – tSPCKr – tSPCKf) /

2 – 3

—

Slave

0.4

0.6

tSPcyc

RSPCK clock rise and

fall time

Master

tSPCKr, tSPCKf —

Slave

—

µs

Data input setup time

Master

tSU

—

Figure 2.34 to Figure

2.39

Slave

—

Data input hold time

Master

(PCLKA

division ratio

set to 1/2)

tHF

—

Master

(PCLKA

division ratio

set to a value

other than

1/2)

tPcyc

—

Slave

—

SSL setup time

Master

tLEAD

N × tSPcyc - 10*1

N × tSPcyc +

100*1

Slave

4 × tPcyc

—

SSL hold time

Master

tLAG

N × tSPcyc - 10*2

N × tSPcyc +

100*2

Slave

4 × tPcyc

—

Data output delay

Master

tOD1

—

6.3

tOD2

—

6.3

Slave

tOD

—

Data output hold time

Master

tOH

—

Slave

—

Successive

transmission delay

Master

tTD

tSPcyc + 2 × tPcyc

8 × tSPcyc + 2

× tPcyc

Slave

4 × tPcyc

MOSI and MISO rise

and fall time

Output

tDr, tDf

—

Input

—

µs

SSL rise and fall time

Output

tSSLr, tSSLf

—

Input

—

µs

Slave access time

tSA

—

Figure 2.38 and

Figure 2.39

Slave output release time

tREL

—

Note:

tPcyc: PCLKA cycle.

RA4E1 Datasheet

2. Electrical Characteristics

R01DS0391EJ0130 Rev.1.30

Jun 6, 2025

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