RA2L2 datasheet(37/108 Pages) RENESAS

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Independent watchdog timer reset

Software reset

Internal reset

tRESWT3

tRESWIW, tRESWIR

Figure 2.9

Reset input timing (2)

2.3.4

Wakeup Time

Table 2.22

Timing of recovery from low power modes (1)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Recovery

time from

Software

Standby

mode*1

High-

speed

mode

Crystal

resonator

connected to

main clock

oscillator

System clock

source is main

clock oscillator (20

MHz)*2

tSBYMC

—

Figure 2.10

External clock

input to main

clock

oscillator

System clock

source is main

clock oscillator (20

MHz)*3

tSBYEX

—

2.4

3.1

µs

System clock source is HOCO

(HOCO clock is 32 MHz)*4

tSBYHO

—

7.4

9.1

µs

System clock source is HOCO

(HOCO clock is 48 MHz)*5

tSBYHO

—

7.3

8.9

µs

System clock source is HOCO

(HOCO clock is 64 MHz)*4

tSBYHO

—

7.4

9.1

µs

System clock source is MOCO (8

MHz)

tSBYMO

—

µs

Note 1. The division ratio of ICLK and PCLKx is the minimum division ratio within the allowable frequency range. The recovery time is

determined by the system clock source.

Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x05.

Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 0x00.

Note 4. The system clock is 32 MHz.

Note 5. The system clock is 48 MHz.

RA2L2 Datasheet

2. Electrical Characteristics

R01DS0445EJ0120 Rev.1.20

Jun 9, 2026

Page 37 of 108

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