F24 datasheet(58/210 Pages) RENESAS

58 / 210 page

RL78/F23, F24

3. ELECTRICAL SPECIFICATIONS (GRADE 3)

R01DS0446EJ0120 Rev.1.20

Page 58 of 207

Dec 31, 2025

(TA = -40 to +105

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

(2/2)

Items

Symbol

Conditions

MIN.

TYP. MAX.

Unit

Supply

current

Notes 1, 3

IDD2

HALT mode Note 2

High-speed on-chip

oscillator clock

operation

fIH = 80 MHz

fCLK = 40 MHz

Note 5

3.4

11.0

fIH = 40 MHz

fCLK = fIH Note 5

2.8

9.5

fIH = 2 MHz

fCLK = fIH Note 5

0.5

1.5

Resonator operation

fMX = 20 MHz

fCLK = fMX Note 6

1.5

5.5

fMX = 2 MHz

fCLK = fMX Note 6

0.3

1.5

Resonator operation

(PLL operation)

(PLL input clock = fMX)

fPLL = 80 MHz,

fMX = 20 MHz

fCLK = 40 MHz

Note 7

3.1

11.0

fPLL = 40 MHz,

fMX = 20 MHz

fCLK = 40 MHz

Note 7

2.8

9.5

fPLL = 40 MHz,

fMX = 4 MHz

fCLK = 40 MHz

Note 7

2.5

9.0

Subsystem clock

operation

fSUB = 32.768

kHz

fCLK = fSUB Note 8

0.7

µA

Low-speed on-chip

oscillator clock

operation

fIL = 15 kHz

fCLK = fIL Note 9

0.7

µA

IDD3

STOP mode Note 4

TA = +25

°C

0.5

µA

TA = +50

°C

4.5

TA = +70

°C

9.0

TA = +105

°C

ISNOZ

SNOOZE mode

DTC operation

6.0

Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input

pin is fixed to VDD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and on-

chip pull-up/pull-down resistors.

2. When HALT mode is entered during fetch from the flash memory.

3. The values below the MAX. column include the peripheral operation current and STOP leakage current.

However, the watchdog timer, LVD circuit, and A/D converter are stopped.

4. When high-speed system clock, subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-

speed on-chip oscillator clock are stopped.

5. When high-speed system clock, subsystem clock, PLL clock, and low-speed on-chip oscillator clock are

stopped.

6. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock

are stopped.

7. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped.

8. When high-speed system clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip

oscillator clock are stopped, and with setting of ADSLP = 1.

9. When high-speed system clock, subsystem clock, PLL clock, and high-speed on-chip oscillator clock are

stopped, and with setting of ADSLP = 1.

Remarks 1. fMX: High-speed system clock frequency

2. fSUB: Subsystem clock frequency

3. fPLL: PLL clock frequency

4. fIH: High-speed on-chip oscillator clock frequency

5. fIL: Low-speed on-chip oscillator clock frequency

6. fCLK: CPU/peripheral hardware clock frequency

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