M7040N datasheet(6/159 Pages) STMICROELECTRONICS

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M7040N

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DEPTH-CASCADING . ...... ...... ....... ...... ....... ...... ....... ...... ...... ...124

Depth-Cascading Up to Eight Devices(One Block) ....... ...... ....... ...... ...... ...124

Depth-Cascading Up to 31 Devices (4 Blocks) .... ....... ...... ....... ...... ...... ...124

Depth-Cascading to Generate a “FULL” Signal.... ....... ...... ....... ...... ...... ...124

Depth-Cascading to Form a Single Block (Figure 93.) ..... ...... ....... ...... ...... ...125

Depth-Cascading Four Blocks (Figure 94.) . ...... ....... ...... ....... ...... ...... ... 126

“FULL” Generation in a Cascaded Table (Figure 95.) ...... ...... ....... ...... ...... ...127

SRAM ADDRESSING . ...... ...... ....... ...... ....... ...... ....... ...... ...... ... 128

Generating an SRAM Bus Address (Table 52.).... ....... ...... ....... ...... ...... ...128

SRAM PIO Access ...... ...... ....... ...... ....... ...... ....... ...... ...... ...128

SRAM READ with a Table of One Device ...... ....... ...... ....... ...... ...... ...128

SRAM READ Access for One Device (Figure 96.) . ....... ...... ....... ...... ...... ...129

SRAM READ with a Table of Up to Eight Devices ...... ...... ....... ...... ...... ...130

Table with Eight Devices(Figure 97.) ..... ...... ....... ...... ....... ...... ...... ...131

SRAM READ Through Device 0 in a Block of EightDevices (Figure 98.).... ...... ...... ...132

SRAM READ Timing for Device 7 in a Block of EightDevices (Figure 99.) . . ...... ...... ...133

SRAM READ with a Table of Up to 31 Devices .. ....... ...... ....... ...... ...... ...134

Table of 31 Devices Made of Four Blocks (Figure 100.) .... ...... ....... ...... ...... ...135

SRAM READ Through Device 0 in a Bank of 31 Devices (Device 0 Timing) (Figure 101.) . . ...136

SRAM READ Through Device 0 in a Bank of 31 Devices (Device 30 Timing) (Figure 102.) . ...137

SRAM WRITEwith a Table of One Device ...... ....... ...... ....... ...... ...... ...138

SRAM WRITEAccess for One Device (Figure 103.) ...... ...... ....... ...... ...... ...139

SRAM WRITEwith a Table of Up to Eight Devices...... ...... ....... ...... ...... ...140

Table with Eight Devices(Figure 104.) .... ...... ....... ...... ....... ...... ...... ... 141

SRAM WRITE Through Device 0 in a Block of Eight Devices (Figure 105.) . . ...... ...... ...142

SRAM WRITETiming for Device 7 in a Block ofEight Devices(Figure 106.). ...... ...... ... 143

SRAM WRITEwith Table(s) of Up to 31 Devices ....... ...... ....... ...... ...... ...144

Table of 31 Devices (Four Blocks) (Figure 107.) . . . ....... ...... ....... ...... ...... ...145

SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 0 Timing) (Figure 108.). . ...146

SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 30 Timing) (Figure 109.). ...147

JTAG (1149.1) TESTING .... ...... ....... ...... ....... ...... ....... ...... ...... ... 148

Supported Operations (Table 53.) . ....... ...... ....... ...... ....... ...... ...... ... 148

TAPDevice ID Register (Table 54.) ...... ...... ....... ...... ....... ...... ...... ...148

PART NUMBERING .. ...... ...... ....... ...... ....... ...... ....... ...... ...... ...149

PACKAGE MECHANICAL INFORMATION . . . ...... ....... ...... ....... ...... ...... ...150

APPENDIX... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ...152

REVISION HISTORY. . ...... ...... ....... ...... ....... ...... ....... ...... ...... ...158

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