M7040N datasheet(74/159 Pages) STMICROELECTRONICS

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M7040N

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Table 37. Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit

Table 38. Shift of SSF and SSV from SADR

144-bit Search on Tables Configured as x144 Using Up to 31 M7040N Devices

The hardware diagram of the search subsystem of

31 devices is shown in Figure 52, page 76. Each

of the four blocks in the diagram represents a

block of eight M7040N devices (except the last,

which has seven devices).The diagram for a block

of eight devices is shown in Figure 53, page 77.

Following are the parameters programmed into

the 31 devices.

First thirty devices (devices 0–29):

CFG = 0101010101010101, TLSZ = 10,

HLAT = 001, LRAM = 0, and LDEV = 0.

Thirty-first device (device 30):

CFG = 0101010101010101, TLSZ = 10,

HLAT = 001, LRAM = 1, and LDEV = 1.

Note: All 31 devices must be programmed with the

same value of TLSZ and HLAT. Only the last de-

vice in the table must be programmed with

LRAM = 1 and LDEV = 1 (Device 30 in this case).

All other upstream devices must be programmed

with LRAM = 0 and LDEV = 0 (Devices 0 through

29 in this case).

The timing diagrams referred to in this paragraph

reference the HIT/MISS assumptions defined in

Table 39, page 75. For the purpose of illustrating

timings, it is further assumed that the there is only

one device with a matching entry in each of the

blocks. Figure 55, page 79 shows the timing dia-

gram for a SEARCH command in the 144-bit-con-

figured table (31 devices) for each of the eight

devices in Block 0. Figure 56, page 80 shows the

timing diagram for SEARCH command in the

72-bit-configured table (31 devices) for all the de-

vices in Block 1 above the winning device in that

block. Figure 57, page 81 shows the timing dia-

gram for the globally winning device (the final win-

ner within its own block and all blocks) in Block 1.

Figure 58, page 82 shows the timing diagram for

all the devices below the globally winning device in

Block 1. Figure 59, page 83, Figure 60, page 84,

and Figure 61, page 85 respectively show the tim-

ing diagrams of the devices above globally win-

ning device, the globally winning device and

devices below the globally winning device for

Block 2. Figure 62, page 86, Figure 63, page 87,

Figure 64, page 88, and Figure 65, page 89 re-

spectively show the timing diagrams of the devices

above the globally winning device, the globally

winning device, and devices below the globally

winning device except the last device (Device 30),

and the last device (Device 30) for Block 3.

# of devices

Max Table Size

Latency in CLK Cycles

1 (TLSZ = 00)

32K x 144-bit

1–8 (TLSZ = 01)

256K x 144-bit

1–31 (TLSZ = 10)

992K x 144-bit

HLAT

Number of CLK Cycles

000

001

010

011

100

101

110

111

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