M7040N datasheet(25/159 Pages) STMICROELECTRONICS

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M7040N

The Command Register

Table 11. Command Register Field Descriptions

Field

Range

Initial

Value

Description

SRST

[0]

Software Reset. If '1,' this bit resets the device, with the same effect as the hardware

reset. Internally, it generates a reset pulse lasting for eight CLK cycles. This bit

automatically resets to a '0' the reset cycle has completed.

DEVE

[1]

Device Enable. If '0,' it keeps the SRAM Bus (SADR, WE_L, CE_L, OE_L, and

ALE_L), SSF, and SSV signals in 3-state condition and forces the cascade interface

output signals LHO[1:0] and BHO[2:0] to '0.' It also keeps the DQ Bus in input mode.

The purpose of this bit is to make sure that there are no bus contentions when the

devices power up in the system.

TLSZ

[3:2]

Table Size. The host ASIC must program this field to configure the chips into a table

of a certain size. This field affects the pipeline latency of the SEARCH and LEARN

operations as well as the READ and WRITE accesses to the SRAM (SADR[23:0],

CE_L, OE_L, WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the search

latency stays constant.

Latency # CLK Cycles

with HIGH_SPEED low

00: 1 device

01: 2-8 devices

10: 9-31 devices

11: Reserved

Latency # CLK Cycles

with HIGH_SPEED high

00: Not supported

01: 1 devices

10: 2-31 devices

11: Reserved

HLAT

[6:4]

000

Latency of Hit Signals. This field adds latency to the SSF and SSV signals during

SEARCH, and ACK signal during SRAM READ access by the following number of

CLK cycles.

000: 0

100: 4

001: 1

101: 5

010: 2

110: 6

011: 3

111: 7

LDEV

[7]

Last device in the cascade. When set, this is the last device in the depth-cascaded

table and is the default driver for the SSF and SSV signals.

In the event of a search failure, the device with this bit set drives the hit signals as

follows:

SSF = 0, SSV = 1

During non-search cycles, the device with this bit set drives the signals as follows:

SSF = 0, SSV = 0

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