M7020R datasheet(37/150 Pages) STMICROELECTRONICS

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M7020R

The logical 68-bit SEARCH operation is shown in

Figure 21, page 39. The entire table consisting of

68-bit entries is compared to a 68-bit word K (pre-

sented on the DQ Bus in both Cycles A and B of

the command) using the GMR and the local mask

bits. The effective GMR is the 68-bit word speci-

fied by the identical value in both even and odd

GMR pairs selected by the GMR Index in the com-

mand’s Cycle A. The 68-bit word K (presented on

the DQ Bus in both Cycles A and B of the com-

mand) is also stored in both even and odd com-

parand register pairs selected by the Comparand

configuration, only the even comparand register

can be subsequently used by the LEARN com-

mand. The word K (presented on the DQ Bus in

both Cycles A and B of the command) is compared

with each entry in the table starting at location “0.”

The first matching entry’s location address, “L,” is

the winning address that is driven as part of the

SRAM address on the SADR[21:0] lines (see

SRAM ADDRESSING, page 126).

The SEARCH command is a pipelined operation

and executes a SEARCH at half the rate of the fre-

quency of CLK2X for 68-bit searches in x68-con-

figured tables. The latency of SADR, CE_L,

ALE_L, WE_L, SSV, and SSF from the 68-bit

SEARCH command cycle (two CLK2X cycles) is

shown in Table 25, page 39.

The latency of a SEARCH from command to

SRAM access cycle is 4 for a single device in the

table and TLSZ = 00. In addition, SSV and SSF

shift further to the right for different values of

HLAT, as specified in Table 26, page 39.

Figure 19. Hardware Diagram for a Table with One Device

DQ[67:0]

CMDV, CMD[8:0]

SSF, SSV

SRAM

BHI[2:0]

LHO[1]

LHI

3210

M7020R

LHO[0]

654

AI05664

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