M7020R datasheet(17/150 Pages) STMICROELECTRONICS

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M7020R

Table 7. AC Timing Parameters with CLK2X

Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VDD = 1.8V.

2. Values are based on 50% signal levels.

3. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 14).

4. These parameters are sampled and not 100% tested, and are based on an AC load of 5pF.

Row

Symbol

M7020R-050

M7020R-066

M7020R-083

Unit

Description(1)

Min

Max

Min

Max

Min

Max

fCLOCK

100

133

166

MHz

CLK2X frequency

tCLK

7.5

CLK2X period

tCKHI

4.0

3.0

CLK2X high pulse(2)

tCKLO

4.0

3.0

CLK2X low pulse(2

tISCH

2.5

Input Setup Time to CLK2X rising edge.(2)

tIHCH

0.6

Input Hold Time to CLK2X rising edge.(2)

tICSCH

4.2

Cascaded Input Setup Time to CLK2X rising

edge.(2)

tICHCH

0.6

Cascaded Input Hold Time to CLK2X rising

edge.(2)

tCKHOV

9.5

8.5

Rising edge of CLK2X to LHO, FULO, BHO,

FULL valid.(3)

tCKHDV

10.0

9.0

Rising edge of CLK2X to DQ valid.(2)

tCKHDZ

1.2

9.5

1.2

9.5

1.2

9.5

Rising edge of CLK2X to DQ high-Z.(4)

tCKHSV

10.0

9.0

Rising edge of CLK2X to SRAM Bus valid.(2)

tCKHSHZ

7.0

6.5

Rising edge of CLK2X to SRAM Bus high-

Z.(2,4)

tCKHSLZ

7.5

7.0

Rising edge of CLK2X to SRAM Bus low-

Z.(2,4)

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