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AT25DF021A-DWFHT bảng dữ liệu(PDF) 38 Page - Renesas Technology Corp

tên linh kiện AT25DF021A-DWFHT
Giải thích chi tiết về linh kiện  2-Mbit, 1.65 V Minimum SPI Serial Flash Memory with Dual-I/O Support
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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AT25DF021A-DWFHT bảng dữ liệu(HTML) 38 Page - Renesas Technology Corp

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DS-AT25DF021A-042 Rev. L
Page 38
8/7/23
© 2023 Renesas Electronics
AT25DF021A Datasheet
Figure 30. Read Manufacturer and Device ID
12.2 Deep Power-Down
During normal operation, the device is placed in the standby mode to consume less power as long as the CS pin
remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to
place the device into an even lower power consumption state called the Deep Power-Down mode.
When the device is in the Deep Power-Down mode, all commands including the Read Status Register command
is ignored with the exception of the Resume from Deep Power-Down command. Since all commands are ignored,
the mode can be used as an extra protection mechanism against program and erase operations.
Entering the Deep Power-Down mode is done by simply asserting the CS pin, clocking in the opcode of B9h, and
then deasserting the CS pin. Any additional data clocked into the device after the opcode are ignored. When the
CS pin is deasserted, the device enters the Deep Power-Down mode within the maximum time of tEDPD.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on
an even byte boundary (multiples of eight bits); otherwise, the device stops the operation and returns to the
standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power-cycle.
The Deep Power-Down command is ignored if an internally self-timed operation such as a program or erase cycle
is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has
been completed in order for the device to enter the Deep Power-Down mode.
Figure 31. Deep Power-Down
SCK
CS
SI
SO
6
0
9Fh
8
7
38
OPCODE
1Fh
43h
00h
MANUFACTURER ID
DEVICE ID
BYTE1
DEVICE ID
BYTE2
EXTENDED
DEVICE
INFORMATION
STRING LENGTH
14
16
15
22
24
23
30
32
31
Note: Each transition
shown for SI and SO represents one byte (8 bits)
High-Impedance
01h
SCK
CS
SI
SO
MSB
ICC
23
1
0
10111001
67
5
4
OPCODE
High-Impedance
Standby Mode Current
Active Current
Deep Power-Down Mode Current
tEDPD



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