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PCI11010C bảng dữ liệu(PDF) 11 Page - Microchip Technology

tên linh kiện PCI11010C
Giải thích chi tiết về linh kiện  PCIe Switch with Integrated Ethernet MAC and Programmable I/O
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PCI11010C bảng dữ liệu(HTML) 11 Page - Microchip Technology

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2025 Microchip Technology Inc. and its subsidiaries
DS00006232A-page 11
PCI11010C
3.0
PIN DESCRIPTIONS AND CONFIGURATION
The device pin diagram for the PCI11010C can be seen in Figure 3-1. Table 3-1 provides a PCI11010C pin assignments
table with reset states. Pin descriptions are detailed in Section 3.1, "Pin Descriptions". Configuration strap descriptions
are detailed in Section 3.2, "Configuration Straps". Programmable function pin descriptions are detailed in Section 3.3,
"Programmable Function Pins". Buffer type and pin reset state definitions are provided in Section 1.2, "Buffer Types"
and Section 1.3, "Pin Reset States", respectively.
FIGURE 3-1:
PIN ASSIGNMENTS
Note: Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
XTALO
XTALI/CLK_IN
Microchip
PCI11010C
(Top View 100-VQFN)
PROG67
PROG66
VSSXTAL
VDDVARIO
PROG65/SMBUS_SDA_PU
PROG64/SMBUS_SCL_PU
PROG70
PROG69
PROG68/SERIAL_SEL_STRAP
PROG1
VDD33
VSSPVTREF
PROG17/PVT1
PROG71
RESET_N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
74
73
51
52
53
54
57
56
55
75
PROG2
PROG3
VDD11XTAL
VDD11
VDD33A1
PROG63/RGMII_TXD3
PROG62/RGMII_TXD2
PROG61/RGMII_TXD1/RMII_TXD1
PROG60/RGMII_TXD0/RMII_TXD0
PROG59/RGMII_TX_CTL/RMII_TX_EN
ENET_RESREF
PROG58/RGMII_TXC/RMII_REF_CLK_OUT
VDD33ENET
VDDRGMII
PROG0
VDD33PVTREF
PCIE_TXP_L0_P0
PCIE_TXM_L0_P0
PCIE_RXP_L1_P0
PCIE_RXM_L1_P0
PCIE_TXP_L1_P0
PCIE_TXM_L1_P0
PCIE_RXP_L0_P0
PCIE_RXM_L0_P0
VDD11
VDD11PA
VDD33PA
VDD11PA
VDD11PA
VDD33PA
VDD11PA
VDD33PA
VDD11PA
E-PAD is VSS



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