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IMXRT1160AXEC bảng dữ liệu(PDF) 79 Page - NXP Semiconductors |
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IMXRT1160AXEC bảng dữ liệu(HTML) 79 Page - NXP Semiconductors |
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79 / 130 page ![]() Electrical characteristics i.MX RT1160 Crossover Processors Data Sheet for Extended Industrial Products, Rev. 4, 06/2025 NXP Semiconductors 79 ENOB Effective number of bits 8,9,10 Single-ended mode Avg = 1 10.0 10.4 — — Avg = 2 10.4 10.6 — — Avg = 16 11.2 11.3 — — Differential mode Avg = 1 11.0 11.2 — — Avg = 2 — — — — Avg = 16 — — — — SINAD Signal to noise plus distortion SINAD = 6.02 x ENOB + 1.76 dB — EG Gain error11 — -0.16 -0.56 %FSV 12 EO Offset error — ±0.01 ±0.02 %FSV 13 lin_ext_leak External channel leakage current — 30 500 nA — EIL Input leakage error RAS * lin_ext_leak mV — tADCSTUP Setup time — 5 — s — 1 The range is from 1.71 V to 1.89 V. 2 Values in this table are based on test with limited matrix samples in lab environment. 3 This resistance is external to the SoC. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 15 Ω analog source resistance. 4 See Figure 35, "Sample time VS. RAS". 5 1 LSB = (VREFH - VREFL) / 2^N, N = 12 6 ADC conversion clock at max frequency and using linear histogram. 7 No missing code 8 Input data used for test is 1 kHz sine wave. 9 Measured at VREFH = 1.8 V and pwrsel = 2. 10 ENOB can be lower than shown, if an ADC channel corrupts other ADC channels through capacitive coupling. This coupling may be dominated by board parasitics. Care must be taken not to corrupt the desired channel being measured. This coupling becomes worse at higher analog frequencies and with switching waveforms due to the harmonic content. 11 Gain error is FSE-ZSE (same as FSE-EO). 12 Error measured at full scale at 1.8 V. 13 Offset error is same as ZSE, error measured at 0 V with zero scale. Table 76. ADC electrical specifications (VREFH = 1.68 V and VADINmax ≤ NVCC_GPIOmax)1 Symbol Description Min Typ2 Max Unit Notes VADIN Input voltage VREFL — NVCC_GPIOmax V — CADIN Input capacitance — 2.25 — pF — RADIN Input resistance — 1 — K — Table 75. ADC electrical specifications (VREFH = VDDA_ADC_1P81 and VADINmax ≤ VREFH)2 (continued) Symbol Description Min Typ Max Unit Notes |
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