DDS39RF12ACK datasheet(72/177 Pages) TI2

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Figure 7-55. RBD Example (lane arrivals do not

straddle zero)

Figure 7-56. RBD Example (lane arrivals straddle

zero)

7.3.7.9 Operation in Subclass 0 Systems

The device can operate with subclass 0 compatibility provided that multi-DAC synchronization and deterministic

latency are not required. With these limitations, the device can operate without the application of SYSREF.

The internal LMFC is automatically self-generated with unknown starting phase. RBD does not need to be

programmed as the elastic buffer is released automatically just after the latest arriving lane begins to write to the

elastic buffer. SYNC is used as normal to initiate the CGS and ILAS.

7.3.7.10 Link Reset

The entire link layer for all lanes is reset any time:

• There is a gearbox FIFO underflow/overflow detected (LANE_ERR[0]) on a lane used by the JESD link

• There is an elastic buffer overflow detected (EB_ERR) on a lane used by the JESD link

• The JESD link goes down (JESD_LINK_DOWN_ALM)

• SYSREF causes clock divider or LMFC/LEMC realignment (REALIGNED)

• The JTimer expires (JTIMER_EXPIRED_ALM)

7.3.8 Alarm Generation

The alarm pin is useful for notifying the host controller of events that may require intervention. Any active alarms

in the SYS_ALM register asserts the alarm output if they are not masked in the ALM_MASK register.

7.4 Device Functional Modes

This section describes the functional modes of the device. Some of the features in this section have been

discussed in further detail in Feature Description.

7.4.1 DUC and DDS Modes

The device contains a DUC mode and a direct digital synthesis (DDS) mode. The data path mode uses complex

(I and Q) data from the JESD interface, interpolates and upconverts it in the DUCs, sums the DUC outputs and

generates the analog signal in the DAC. In DDS mode, the DUC NCOs are used directly to generate tones

without requiring input data.

The list below summarized how DDS mode differs from DUC mode:

DDS39RF12, DDS39RFS12

SBASB21 – SEPTEMBER 2024

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