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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DDS39RF12ACK bảng dữ liệu(PDF) 29 Page - Texas Instruments |
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DDS39RF12ACK bảng dữ liệu(HTML) 29 Page - Texas Instruments |
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29 / 177 page  6.9 Switching Characteristics Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 12 GHz, IFS_SWITCH = 20.5 mA, single tone amplitude = 0 dBFS, Dither and DEM enabled, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT JESD204C SERDES INTERFACE 6SRX-/+, 14SRX-/+ fSERDES SERDES bit rate(4) .78125 12.8 Gbps UI Unit Interval 78.125 1280 ps LATENCY TDAC DAC clock period 1 / fCLK s tPD(RX) Serdes RX analog propagation delay Serdes RX analog propagation delay 215 ps tPDI Input clock rising edge cross-over to output sample cross-over Input clock rising edge cross-over to output sample cross-over 500 ps tDACLAT Digital path latency from SYSREF rising edge to DAC output See XLS Calculator tRELEASE Latency from SYSREF rising edge to elastic buffer release See XLS Calculator tRXIN Latency from SERDES Input to elastic buffer release See XLS Calculator tTXEN_OUTPUT TXENABLE rising edge to data output of DAC FAST_TX_EN = 0 varies(1) CLK Cycles FAST_TX_EN=1 and QUIET_TX_DISABLE=0 93 FAST_TX_EN=1 and QUIET_TX_DISABLE=1 133 tTXEN_MUTE TXENABLE falling edge to DAC output muted QUIET_TX_DISABLE=0 93 QUIET_TX_DISABLE=1 133 tTXEN_PW Required TXENABLE pulse width FAST_TX_EN = 0(2) 102 FAST_TX_EN = 1(3) 20 SERIAL PROGRAMMING INTERFACE Fs_c serial clock frequency 15.625 MHz Fs_cts serial clock frequency temp sensor TS_TEMP register read 1 MHz tP serial clock period 64 ns tPH serial clock pulse width high 32 ns tPL serial clock pulse width low 32 ns tSU SDI setup time 30 ns tH SDI hold time 3 ns tIZ SDI TRI-STATE 3 ns tODZ SDO driven to TRI-STATE 200 fF load 5 ns tOZD SDO TRI-STATE to driven 200 fF load 3 ns tOD SDO output delay 200 fF load 3 ns tCSS SCS setup 30 ns tCSH SCS hold 3 ns tRS RESET setup to serial clock RESET high 30 ns tRH RESET hold to serial clock RESET high 30 ns tIAG Inter-access gap 30 ns FAST RECONFIGURATION (FR) INTERFACE FFRCLK FRCLK frequency 200 MHz tFRCLK_P FRCLK period 5 ns tFRCLK_PH FRCLK pulse width high 2 ns www.ti.com DDS39RF12, DDS39RFS12 SBASB21 – SEPTEMBER 2024 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DDS39RF12 DDS39RFS12 |
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