TPS3435CGLEFDDFR datasheet(6/37 Pages) TI2

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Table 5-1. Pin Functions

NAME

PIN NUMBER

I/O

DESCRIPTION

PINOUT

CRST

—

Programmable WDO assert time pin. Connect a capacitor between this pin

and GND to program the WDO assert time period. See Section 7.3.3 for more

details.

CWD

—

Programmable watchdog timeout input. Watchdog timeout is set by connecting a

capacitor between this pin and ground. See Section 7.3.1.1 for more details.

GND

—

Ground pin

—

Manual reset pin. A logic low on this pin asserts the WDO output. See Section

7.3.2 for more details.

WDO

Watchdog output. Connect WDO to VDD using pull up resistance when using

open drain output. WDO is asserted when a watchdog error occurs or MR pin is

driven LOW. See Section 7.3.3 for more details.

SET0

Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling

and enable-disable the watchdog; see Section 7.3.1.4 for more details.

SET1

—

Logic input. SET0, SET1, and WD-EN pins select the watchdog timer scaling

and enable-disable the watchdog; see Section 7.3.1.4 for more details.

VDD

Supply voltage pin. For noisy systems, connecting a 0.1µF bypass capacitor is

recommended.

WD-EN

—

Logic input. Logic high input enables the watchdog monitoring feature. See

Section 7.3.1.2 for more details.

WDI

Watchdog input. A falling transition (edge) must occur at this pin before the

timeout expires in order for WDO to not assert. See Section 7.3.1 for more

details.

TPS3435-Q1

SLVSGF0B – OCTOBER 2022 – REVISED MARCH 2025

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