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TPS3435CGLEFDDFR bảng dữ liệu(PDF) 26 Page - Texas Instruments |
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TPS3435CGLEFDDFR bảng dữ liệu(HTML) 26 Page - Texas Instruments |
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26 / 37 page ![]() 8.2.1.2.4 Calculating the WDO Pullup Resistor The TPS3435-Q1 uses an open-drain configuration for the WDO output, as shown in Figure 8-2. When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to make sure that VOL is below the maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum WDO pin current (ISink), and VOL. The maximum VOL is 0.3V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3V with ISink kept below 2mA for VDD ≥ 3V and 500μA for VDD = 1.5V. For this example, with a VPU =VDD = 1.5V, a resistor must be chosen to keep ISink below 500μA because this value is the maximum consumption current allowed. To make sure this specification is met, a pullup resistor value of 10kΩ was selected, which sinks a maximum of 150μA when WDO is asserted. WDO VDD WDO CONTROL Figure 8-2. Open-Drain WDO Configuration 8.3 Power Supply Recommendations This device is designed to operate from an input supply with a voltage range between 1.04V and 6V. An input supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is to place a 0.1µF capacitor between the VDD pin and the GND pin. 8.4 Layout 8.4.1 Layout Guidelines Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a 0.1µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected. • Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1µF ceramic capacitor as near as possible to the VDD pin. • Place CCRST capacitor as close as possible to the CRST pin. • Place CCWD capacitor as close as possible to the CWD pin. • Place the pullup resistor on the WDO pin as close to the pin as possible. TPS3435-Q1 SLVSGF0B – OCTOBER 2022 – REVISED MARCH 2025 www.ti.com 26 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TPS3435-Q1 |
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