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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LMK05028RGCT.B bảng dữ liệu(PDF) 70 Page - Texas Instruments |
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LMK05028RGCT.B bảng dữ liệu(HTML) 70 Page - Texas Instruments |
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70 / 94 page  7.5.9 EEPROM Start-Up Mode Default Configuration The device is factory pre-programmed with the following EEPROM default configuration. Table 7-10. LMK05028 Default Configuration SYSTEM CLOCKS FREQUENCY (Hz) INPUT TYPE 0-PPM REF CLK XO 48,000,000 DC-DIFF(ext. term) XO TCXO - CLOCK INPUTS FREQUENCY (Hz) DPLL REF MUX INPUT TYPE IN0 156,250,000 DPLL 1,2 AC-DIFF(ext. term) IN1 156,250,000 DPLL 1,2 AC-DIFF(ext. term) IN2 27,000,000 DPLL 1,2 AC-DIFF(ext. term) IN3 10,000,000 DPLL 1,2 AC-DIFF(ext. term) DPLL1 INPUT SELECT MODE MANUAL REGISTER SELECTION DPLL1 INPUT AUTO PRIORITY Auto Revertive IN0 IN0 1st IN1 2nd IN2 3rd IN3 4th DPLL2 INPUT SELECT MODE MANUAL REGISTER SELECTION DPLL2 INPUT AUTO PRIORITY Auto Revertive IN0 IN0 1st IN1 2nd IN2 3rd IN3 4th CLOCK OUTPUTS FREQUENCY (Hz) OUTPUT MUX OUTPUT TYPE OUT0 322,265,625.0 PLL 1 AC-LVDS OUT1 122,880,000.0 PLL 2 AC-LVDS OUT2 122,880,000.0 PLL 2 AC-LVDS OUT3 122,880,000.0 PLL 2 AC-LVPECL OUT4 122,880,000.0 PLL 2 AC-LVPECL OUT5 122,880,000.0 PLL 2 AC-LVDS OUT6 122,880,000.0 PLL 2 AC-LVDS OUT7 322,265,625.0 PLL 1 AC-LVDS PLL CONFIGURATION PLL MODE REF-DPLL BW (Hz) TCXO-DPLL BW (Hz) PLL1 2-loop (REF-DPLL) 100 - PLL2 2-loop (REF-DPLL) 100 - REF INPUT MONITORS (1) VALIDATION TIMER (s) FREQ DET VALID (ppm) FREQ DET INVALID (ppm) IN0 0.1 - - IN1 0.1 - - IN2 0.1 - - IN3 0.1 - - REF INPUT MONITORS (2) LATE DETECT WINDOW (μs) EARLY DETECT WINDOW (μs) IN0 - - IN1 - - IN2 - - IN3 - - LMK05028 SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025 www.ti.com 70 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: LMK05028 |
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