LMK05028RGCT.B datasheet(53/94 Pages) TI2

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7.3.17 Zero-Delay Mode (ZDM) Configuration

Zero-delay mode can be enabled to achieve zero phase delay between the selected reference input clock and

the output clocks of a DPLL. As shown in Figure 7-35 and Figure 7-36, DPLL1 supports zero-delay for OUT4/5,

OUT6, and OUT7, while DPLL2 supports zero-delay for OUT0, OUT1, and OUT2/3. Any output that requires the

zero-delay feature must be derived from the P1 (primary) post-divider of the PLL and have zero-delay enabled

(DPLLx_ZDM_EN bit = 1). Then, one of the outputs per DPLL can be selected as the primary zero-delay output

(by O_CHx_y_ZERODLY_EN bit). Other outputs that need zero-delay can be synchronized with the primary

zero-delay output by comprising a SYNC group (see Output Synchronization (SYNC)). ZDM and DCO mode

cannot be enabled at the same time within a PLL channel.

When the DPLL is acquiring lock to the reference input, the initial phase lock is governed by the DPLL fastlock

bandwidth. Once phase lock is detected, the final output phase alignment with the input reference is governed

by the normal DPLL loop bandwidth. The same phase lock and alignment process also occurs when exiting

holdover or after a switchover event.

PLL1

DPLL1 ZDM

Channel

OUT[4:7] Channels (x3)

ZDM

Feedback

÷OD

ZDM off

INx

OUT4/5

OUT6

OUT7

O_CH4_7_ZERODLY_EN

DPLL1_

ZDM_EN

OUT

÷R

To TDC for

phase offset

cancellation

fVCO1/P1

Figure 7-35. DPLL1 ZDM Configuration for OUT4 to OUT7

PLL2

DPLL2 ZDM

Channel

OUT[0:3] Channels (x3)

÷OD

ZDM off

OUT2/3

OUT1

OUT0

O_CH0_3_ZERODLY_EN

DPLL2_

ZDM_EN

ZDM

Feedback

OUT

INx

÷R

fVCO2/P1

To TDC for

phase offset

cancellation

Figure 7-36. DPLL2 ZDM Configuration for OUT0 to OUT3

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LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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