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LMK05028RGCT.B bảng dữ liệu(PDF) 69 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM
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7.5.8 Read EEPROM
The contents of the EEPROM can be read back, one word at a time, starting with that of the requested address
through the following sequence. This sequence can be used to verify the contents written to EEPROM after an
EEPROM program cycle.
1. Write the most significant 5 bit of the EEPROM address in R169 (MEMADR byte 1) and write the least
significant 8 bits of the EEPROM address in R170 (MEMADR byte 0).
2. The EEPROM data located at the address specified in the step above can be obtained by reading R171
(NVMDAT byte) in the same register transaction.
• Any additional access that is part of the same transaction causes the EEPROM address to be
incremented and a read takes place of the next EEPROM address.
• Byte or Block read transfers from R171 can be used to read the entire EEPROM map sequentially from
Byte 0 to 508 (509 bytes total).
• Access to EEPROM terminates at the end of current register transaction.
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LMK05028
SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025
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