LMK05028RGCT.B datasheet(24/94 Pages) TI2

tên linh kiện	LMK05028RGCT.B

Giải thích chi tiết về linh kiện	LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM

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1. Below BWREF-DPLL, the REF input noise contributes to output.

2. Above BWREF-DPLL, the REF input noise is attenuated by REF-DPLL bandwidth with up to 60-dB/decade

roll-off.

3. Below BWTCXO-DPLL, the OCXO noise and TDC noise of the TCXO-DPLL determine the output noise here.

The close-in phase noise is –112 dBc/Hz at 100-Hz offset.

4. Above BWTCXO-DPLL, the OCXO noise is attenuated. Below BWAPLL, the APLL noise dominates as the XO

noise contribution is much lower.

5. Above BWAPLL, the VCO noise dominates and the XO noise is attenuated.

6. AC-LVPECL output noise floor is -163 dBc/Hz at 10-MHz offset.

REF-DPLL

5 Hz

TCXO-DPLL

400 Hz

APLL

500 kHz

Output Phase Jitter = 160-fs RMS (12 kHz to 20 MHz)

AC-LVPECL output, fIN = 25 MHz, fTCXO = 10 MHz (OCXO), fXO = 48.0048 MHz, fTCXO-TDC = 20 MHz

Figure 7-5. 122.88-MHz Output Phase Noise (3-Loop) With Phase Noise of External Inputs

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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LMK05028RGCT.B bảng dữ liệu(PDF) 24 Page - Texas Instruments