LMK05028RGCT datasheet(72/94 Pages) TI2

72 / 94 page

HW_SW_CTRL = 1

GPIO[3:0] = 0000b to 1111b

(Select ROM Page)

Start-up Mode?

(sample pin states)

Device Block

Configuration

Registers initialized from EEPROM/ROM (hard reset only).

2C/SPI, Control, Status pins activated.

All blocks reset to initial states.

VCO Calibration

See DPLL Modes and

Input Selection

Flowcharts

EEPROM + I

(Soft Pin) Mode

Power-On Reset

(POR)

PDN?

(Hard reset)

HW_SW_CTRL = 0

GPIO[2:1] = 00b to 11b

(Select I2C Addr.)

EEPROM + SPI

(Soft Pin) Mode

HW_SW_CTRL = Float

STATUS[1:0] = Float

ROM + I

(Hard Pin) Mode

Outputs locked to XO frequency.

Outputs with DPLL auto-mute disabled are un-muted.

Outputs are auto-SYNCed if enabled.

Outputs muted

Soft reset

RESET_SW: 0

XO Detected

Input Monitoring (fastest to slowest detector):

1. Missing and/or Early clock detector

2. Amplitude or Slew rate detector

3. Frequency (ppm) detector

4. After enabled detectors are valid, validation timer

starts and must finish for input to be qualified.

TCXO Detected

TCXO-DPLL Locked

(Free-run from

TCXO)

Outputs locked to TCXO/OCXO frequency.

Skip step if 2-loop REF-DPLL mode is

configured (TCXO-DPLL is not used).

REF-DPLL

Lock Acquisition

APLL Locked

(Free-run from XO)

Ref. Input

Validation

REF-DPLL

Locked

Fastlock bandwidth temporarily asserted

during lock acquisition, if enabled.

Outputs locked to selected input clock frequency.

Outputs with DPLL auto-mute enabled are un-muted.

The configured DPLL loop bandwidth is asserted.

DPLL frequency- and phase-lock detectors are monitored.

If Zero-Delay Mode (ZDM) is enabled, output will have

deterministic input-to-output phase relationship.

TCXO-DPLL

DCO Mode control

available

2-loop TCXO-

DPLL mode

REF-DPLL modes

Device POR

Configuration Sequence

PLL Initialization Sequence

REF-DPLL

DCO Mode control

available (ZDM must be

disabled)

Valid Input Selected

CAL Done

Figure 8-1. Device Start-Up Sequence

LMK05028

SNAS724B – FEBRUARY 2018 – REVISED FEBRUARY 2025

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